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| ? multiplexes/demultiplexes 28 ds1 signals to/from a ds3 signal integrated dejitter buffers to gr-499-core for all receive ds1 outputs, with bypass option m13 or c-bit parity format mode operation febe, c, or p-bit parity error insertion capability ds3 idle signal generators ds1 idle signal (qrs, ais or esf) generators ds3 los, lof, p-bit parity, c-bit parity, ais and idle detectors integrated pmdl controller receive or transmit ds1 los detectors ds2 lof detectors external interface for receiving 14 c-bits and transmitting either 13 or 14 c-bits based on a control bit setting ds3 and ds2 x-bit access ds3 transmit and receive selectable ais generation and detection supports intel, motorola, or multiplexed microprocessor interfaces, and includes interrupt capability ds2 transmit/receive x-bit control/status 8 or 16-bit wide performance counters reset lead test access port for boundary scan single +5v, 5% power supply 208-lead small outline plastic bga package or 208-lead pqfp package (for m13e replacement) the m13x cmos vlsi device provides the functions needed to multiplex and demultiplex 28 independent ds1 signals to and from a ds3 signal with either an m13 or c-bit frame format. it includes some enhanced features relative to the m13e device. a lead (m13x ) is provided for selecting functional and software backwards compatibility with the m13e device (txc-03303). the m13x line side signals typically interface with a transwitch art, arte or dart device, a ds3lim-sn module or other ds3 line circuitry. ter- minal side signals interface with commercially available ds1 line interface devices or a transwitch t1fx8 device for ds1 framing. the output ds1 signals can optionally be dejittered via integrated dejitter buffers (djbs). the djbs meet and exceed the require- ments specified in gr-499-core, 1998. the m13x provides an external transmit (13 or 14 bits) and receive (14 bits) interface for the 21 c-bits while operating in the c-bit parity mode. the feac channel (c3) can be accessed via the external interface or the m13x memory. an integrated pmdl controller is provided for transmitting and receiving hdlc encapsulated pmdl messages. buffering of pmdl messages is provided in the transmit and receive directions. message lengths of arbitrary size can be transmitted or received. the m13x memory map contains up to 64 8-bit register locations for software control, performance counters, and alarm reporting. the microprocessor interface provides for connection to an intel or motorola-compatible microprocessor, or for use of a multiplexed address/data bus. an interrupt lead with programmable polarity is provided. single-board m13 multiplexer compact add/drop mux fractional t3 channelized t3 document number: TXC-03305-mb ed. 4, september 2000 copyright ? 2000 transwitch corporation m13x is a trademark of transwitch corporation transwitch and txc are registered trademarks of transwitch corporation data sheet m13x device ds3/ds1 mux/demux, enhanced features TXC-03305 +5v ds1 clock and data channel 1 i/o ds3 receive clock and data ds3 transmit microprocessor address strap c-bits i/o data, clock, ds3/ds1 mux/demux, m13x clock and data and frame ds1 clock and data channel 28 i/o bus enhanced features terminal side line side leads te s t access por t TXC-03305 m13x lead applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com www.datasheet.in
- 2 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet table of contents section page block diagram ................................................................................................................. .. 4 block diagram description ................................................................................................ 5 lead diagrams ................................................................................................................. .8 lead descriptions ........................................................................................................... 10 power supply, ground, and no connect ................................................................. 10 ds1 receive interfaces ............................................................................................ 11 ds1 transmit interfaces .......................................................................................... 13 ds3 interface ............................................................................................................ 15 microprocessor interface .......................................................................................... 16 transmit c-bit interface ............................................................................................ 20 control leads ........................................................................................................... 21 external clock .......................................................................................................... 21 test access port ...................................................................................................... 22 scan test leads ....................................................................................................... 22 absolute maximum ratings and environmental limitations .......................................... 23 thermal characteristics .................................................................................................. 23 power requirements ....................................................................................................... 23 input, output and input/output parameters .................................................................... 24 timing characteristics ..................................................................................................... 26 operation ..................................................................................................................... ... 39 m13x lead ............................................................................................................... 39 resets ...................................................................................................................... 40 integrated djb devices ............................................................................................ 41 jitter tolerance ......................................................................................................... 42 jitter transfer ........................................................................................................... 45 jitter generation ....................................................................................................... 48 jitter enhancement ................................................................................................... 48 residual jitter ........................................................................................................... 48 interrupts .................................................................................................................. 49 pmdl operation ....................................................................................................... 50 counters ................................................................................................................... 55 c-bit interfaces ......................................................................................................... 56 test access port ...................................................................................................... 57 software initialization sequence ..................................................................................... 66 system considerations ............................................................................................. 66 memory map ................................................................................................................... 6 7 memory map descriptions .............................................................................................. 69 application diagram ........................................................................................................ 95 package information ....................................................................................................... 96 ordering information ....................................................................................................... 98 related products ............................................................................................................. 9 8 standards documentation sources .............................................................................. 100 list of data sheet changes .......................................................................................... 102 documentation update registration form * ............................................................. 106 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. www.datasheet.in - 3 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet list of figures figure page 1m13x TXC-03305 block diagram ................................................................................... 4 2c-bit assignments ........................................................................................................... 7 3m13x TXC-03305 lead diagram for pbga package ..................................................... 8 4m13x TXC-03305 lead diagram for pqfp package ..................................................... 9 5ds3 receive timing ......................................................................................................26 6ds3 transmit timing ..................................................................................................... 27 7ds1 receive timing with djbs disabled ....................................................................... 28 8ds1 receive timing with djbs enabled ....................................................................... 28 9ds1 transmit timing ......................................................................................................29 10c-bit receive interface timing..................................................................................... 30 11c-bit transmit interface timing ................................................................................... 31 12microprocessor read cycle timing - multiplexed interface ........................................ 32 13microprocessor write cycle timing - multiplexed interface ........................................ 33 14microprocessor read cycle timing - intel interface .................................................... 34 15microprocessor write cycle timing - intel interface .................................................... 35 16microprocessor read cycle timing - motorola interface ............................................ 36 17microprocessor write cycle timing - motorola interface ............................................. 37 18boundary scan timing ................................................................................................ 38 19m13x reset structure ................................................................................................. 40 20ds1 input jitter tolerance ........................................................................................... 43 21ds3 input jitter tolerance ........................................................................................... 44 22ds3 to ds1 interface jitter transfer limits ................................................................. 46 23ds1 to ds1 jitter transfer limits ................................................................................ 47 24hdlc format .............................................................................................................. 50 25boundary scan schematic .......................................................................................... 58 26example channelized t3 application .......................................................................... 95 27m13x TXC-03305 208-lead plastic ball grid array package .....................................96 28m13x TXC-03305 208-lead plastic quad flat package ............................................ 97 www.datasheet.in - 4 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet block diagram a block diagram for the m13x device is shown in figure 1 below. figure 1. m13x TXC-03305 block diagram ds3 frame sync ds3dr ds3cr s5 ds3dt ds3ct dr1 cr28 cr1 cdt cfmt cckt s7 s6 ds3 destuffing/pmdl ds1 outputs ds2 sync/destuff 1 dr28 dt1 ct28 ct1 dt28 gnd vdd 28 1 7 ds2 framing/stuffing 1 7 ds3 framing/stuffing/pmdl cdcct cdr cfmr cckr cdccr dlen xck alarm/status control ds3 local loopback ds1 input 1 28 micro- i/o and memory map outdis micro- processor interface processor test access port tms tdi tdo tck trs djb ds1 local loopbacks txfrm hreset m13x www.datasheet.in - 5 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet block diagram description figure 1 shows a simplified block diagram of the m13x and its signal leads. the m13x is packaged in a 208- lead small outline plastic ball grid array (pbga) package or a 208-lead plastic quad flat package (pqfp). the pqfp version is intended to be used as a replacement for transwitch ? s m13e device (txc-03303-aipq) and is not recommended for new designs. the pbga version is intended for new designs. the m13x in the pbga or pqfp packages, with the exception of the boundary scan, can be configured to be functionally compatible with, and have the same memory map as, the m13e device, by applying a high to the m13x lead. the enhanced features included in the m13x can be enabled by applying a low to the m13x lead. these enhanced m13x features are: transmit/receiv e pmdl (path maintenance data link) controller interrupt request lead with programmable polarity and associated interrupt mask bits integrated dejitter buffer (djb) on all receive ds1 outputs with optional bypass capability 16-bit performance counters. new bit in register 1dh does not become set to one again after it is cleared when a constant feac message is received. when the m13x lead is set to high, the m13x enhanced features listed above are disabled and cannot be accessed. in the receive direction, ds3 data (ds3dr) is clocked into the m13x on rising edges of the ds3 input clock (ds3cr). the data and clock signals may be derived from any line interface unit such as transwitch ? s art, arte, dart or ds3lim-sn, or from other line circuitry. the ds3 frame sync block searches for and locks to the ds3 frame, as specified in bellcore gr-499-core ? transport system generic requirements, ? and in ansi t1.107-1995. the m13x receiver monitors the ds3 signal for out of frame, loss of signal, a ds3 ais, ds3 idle signal, p-bit parity, the state of the x-bits, and loss of clock. the ds3 ais detection mechanism is software selectable, with a choice of six detectors. these range from full compliance to t1.107-1995 to unframed all ones ais detection. control bits are also provided in mem- ory which allow all, some of, or none of the ds3 alarms to cause the insertion of ais into the receive ds1 channels. in the m13 format mode, destuffing from ds3 to ds2 is performed based on the states of the c-bits in the ds3 subframes. if two or three of the c-bits in a subframe are ones, the associated stuff bit is interpreted as being a stuff bit and is removed from the data stream and discarded. in the c-bit parity mode, the c-bits are allocated for network performance. the m13x performs far end alarm and control (feac) detection, c-bit parity error detection, and far end block error (febe) detection. feac loopback requests and alarm/status information are provided in the memory map. in addition, the states of 14 c-bits (c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21) are provided at a serial inter- face (cdr), along with an output clock signal (cckr), framing pulse (cfmr), and data link indicator pulse (cdccr). the data link indicator pulse identifies the location of the data link bits, c13, c14, and c15. if the m13x lead is tied low, the receive pmdl (path maintenance data link) controller can be enabled via a control bit. the receive pmdl controller is used to extract pmdl messages of any length. fcs error detection, abort detection, end of message, start of message, invalid frame detected, and receive pmdl fifo status can be monitored via the microprocessor interface. the m13x synchronizes and extracts the 28 ds1 channels from the seven ds2 channels. each of the ds2 channels is monitored for out of frame. the m13x may generate ais in each of the ds1 signal tributaries cor- responding to the ds2 channel(s) that lost frame, depending on the ds1 ais alarm insertion control bits. ds2 to ds1 destuffing is based on the states of the three c-bits in each ds2 subframe. if two or three of the c-bits in one of the ds2 subframes are ones, the stuff bit for that subframe is discarded. in the m13 format mode, the ds2 c-bits or stuffing bits are used for ds1 remote loopback requests for either the m13 or c-bit parity format www.datasheet.in - 6 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet modes. the m13x provides control bits in the memory map for selecting the remote loopback detection mech- anism. the destuffing operation is still active during loopback request and operation. in addition to ds2 syn- chronization, destuffing, and remote loopback request detection, the m13x also extracts the seven ds2 x-bits and provides them to a register. an option is provided that allows the received or transmitted ds1 channels to be monitored for loss of signal. receive data for each of the ds1 channels (drn) is clocked out of the m13x on rising edges of the associated clock signal (crn), where n = 1 - 28. in addition, the m13x provides a stable ds1 clock signal for the data sig- nals received during ais periods. when the m13x lead is held low, dejitter buffers (djbs) can be enabled via a control bit to dejitter the receive ds1 outputs. the djbs meet and exceed gr-499-core specifications. in the transmit direction, ds1 transmit data (dtn) is clocked into the m13x on rising edges of the clock input (ctn) for each of the 28 ds1 channels. a ds1 input block, which consists of a fifo and supporting logic, is provided for each ds1 channel. under software control, the m13x can invert the transmit data signals, or the clock signals, for all 28 ds1 channels. the data inversion feature provides compatibility with certain t1 line interface devices, while the clock inversion feature allows back-to-back m13x operation. the ds1 input block is also used to insert one of three idle patterns from a common generator into a ds1 bit stream, under software control. the selection of the idle pattern is common to all 28 ds1 channels. the idle patterns are: a qrs, an extended super frame ds1 (esf) format with all ones in ds0 channels 1 through 24, and an ais format (all ones). each ds1 signal is multiplexed into the respective ds2 frame, with the stuff bits inserted based on the fill level of an internal fifo. when the fill of the fifo drops below half full, a stuff bit is inserted into the ds1 bit stream in the ds2 signal. the ds2 signal is formed by combining four ds1 signals. in each frame there are 287 data bit positions and one stuff bit per ds1 channel (for a ds1 total of 1152 bits) and 24 overhead bits, for a frame total of 1176 bits. the overhead bits are used for framing, x-bit channel and stuff control. the ds3 signal is partitioned into m-frames of 4760 bits each. the m-frames are divided into seven m-sub- frames having 680 bits each. each m-subframe is further divided into eight blocks of 85 bits each. each block uses 84 bits for payload and one bit for frame overhead. there are 56 overhead bits in each m-frame: the m- frame alignment uses three bits, the m-subframe alignment (f-bits) uses 28 bits, 21 bits are defined as c-bits, two bits are assigned for parity, and two bits are assigned for the x-bit channel. a frame synch input, txfrm , is provided and can optionally be used to align the ds3 overhead bits in the ds3dt output. the ds3 frame is constructed and timed according to the operating mode, i.e., c-bit parity mode or m13 format mode. in the c-bit parity mode, all seven of the ds2 stuff bits are always fixed as stuff, resulting in 7 pseudo ds2 frames of 671 bits per ds2 frame in each ds3 frame, for a ds2 rate of 6.3062723 mbit/s. since stuffing always occurs, the 21 c-bits are assigned for other functions, as shown in figure 2. a c-bit interface is pro- vided for transmitting 13 or 14 c-bits (c2, c3-depending on the state of bit 7 of register 19h (c3clki), c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, c21). the external transmit c-bit interface consists of a serial data input (cdt), an output clock (cckt), a data link indicator pulse (cdcct), and an output framing pulse (cfmt). the data link indicator pulse identifies the location of the three data link bits, c13, c14, and c15. in addition, a control bit is provided in the memory map which enables the m13x to generate an extra clock cycle during the c3 bit time. when the m13x lead is tied low, the transmit pmdl controller can be enabled through software control. the transmit pmdl controller supports transmission of hdlc (high level data link control) encapsulated messages of arbitrary length. interrupt request bits are provided for signaling transmit pmdl fifo and message status. when the transmit pmdl controller is enabled, c13, c14, and c15 on the transmit c-bit interface are ignored; instead, c13, c14, and c15 are sourced from the transmit pmdl controller. a receive c-bit interface is provided for extraction of 14 c-bits (c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, c21). the receive c-bit interface consists of a serial data output (cdr), an output clock (cckr), a data link indicator pulse (cdccr), and an output framing pulse (cfmr). the data link indicator pulse identifies the location of the three data link c-bits, c13, c14, and c15. www.datasheet.in - 7 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet notes: * these bits are always provided at the c-bit interface in the c-bit mode. ** this bit is always provided at the receive c-bit interface in the c-bit mode. this bit is optionally processed at the transmit c-bit interface. *** these bits are always provided at the receive c-bit interface in the c-bit mode. in the transmit direction these bits can optionally be supplied via the integrated pmdl controller. figure 2. c-bit assignments of the eight remaining c-bits, c1 is used as an identification channel; c3 is defined as a far end alarm and control (feac) bit and is controlled via the memory map; c7, c8, and c9 are used for c-bit parity; and the remaining three bits, c10, c11, and c12, are used to transmit a febe indication. a febe is automatically transmitted if a c-bit parity error or framing error is received. fixed ds2 to ds3 stuffing is used for m23 multiplexing at a rate of seven stuffs for every 18 ds3 stuff opportu- nities. this yields a ds2 frequency of +2.6 ppm above the desired frequency of 6.312 mbit/s. after adding this to the tolerance of the ds3 clock signal, 20 ppm, the frequency is still within the 32 ppm allowed for a ds2 signal. under software control, the m13x can generate ds3 idle and ais signals, and loop back the transmitted ds3 signal to the receiver for test purposes. other functions provided by the m13x include: ds1 loopback capability, and transmit clock failure protection. the microprocessor interface is selectable via two external hardware straps. interface options are: multiplexed, intel compatible, or motorola compatible. an interrupt request lead with programmable polarity is provided and can be used when the m13x lead is tied low. c1 c2* c3** c4* c5* c6* c7 c8 c9 c10 c11 c12 c13*** c14*** c15*** c16* c17* c18* c19* c20* c21* c1 = c-bit parity mode c2 = reserved c3 = far end alarm and control (feac) not defined, set to 1 c-bit parity bits far end block error (febe) maintenance data link (28 kbit/s) not defined, set to 1 not defined, set to 1 www.datasheet.in - 8 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet lead diagrams the m13x is available in both plastic ball grid array (pbga) and plastic quad flat package (pqfp) packages, as shown in figures 3, 4, 27 and 28. figure 3. m13x TXC-03305 lead diagram for pbga package gnd a r p n m l k j h g f e d c b 1 2 3 5 6 7 8 9 10 11 12 13 14 15 hreset dlen dr26 dr28 m13x cr25 dt9 vdd ct15 dt20 ds3ct ct18 ct24 dt22 ct21 dt28 ct27 dt26 dt27 gnd dt21 dt23 dt17 nc ct20 dt15 nc ct10 dt25 ct26 ct28 ct22 dt24 vdd ct13 dt14 dt16 ct9 ct25 vdd ds3dt ct17 dt19 dt13 ct14 ct16 nc cfmt cckt xck cdt s5 vdd s6 s7 a/d1,d1 a/d3,d3 a/d7,d7 vdd ale sel nc nc rd ,rd/wr wr ds3cr cfmr cdccr nc a3 a0 cr2 dr4 dr6 mtest cr8 dr12 dr14 cr15 cr17 cr28 dr19 dr25 cr16 cr14 dr13 dr11 cr9 nc dr7 dr5 cr3 a4 dr1 gnd ds3dr cckr cr1 cdr nc cr5 cr7 dr8 dr10 cr10 cr12 nc t 16 cr4 a1 a2 gnd a5 a6 a7 a/d6,d6 a/d5,d5 a/d4,d4 a/d2,d2 a/d0,d0 scan_en ct23 dt18 ct19 cdcct cr27 nc dr27 vdd dr18 dr16 4 cr26 cr24 cr22 cr20 dt3 ct1 dt7 dt5 outdis p0 scan_shift tck cr23 cr21 cr19 ct4 ct2 dt8 dt6 dt12 gnd tdo tdi tms txfrm dt11 ct12 ct11 gnd dt10 ct5 ct7 nc dr21 dt2 dt4 vdd dr23 trs p1 rdy/dtack gnd ct6 ct8 dt1 ct3 dr20 dr22 dr24 int/irq vdd dr2 dr3 cr6 vdd dr9 cr11 cr13 dr15 dr17 cr18 all 16 of these balls are gnd note: this a bottom view of the m13x 208-lead plastic ball grid array package. all leads are solder balls. some lead symbols may be abbreviated. see figure 27 for package dimension information. this diagram is rotated relative to the bottom view shown in figure 27. www.datasheet.in - 9 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 4. m13x TXC-03305 lead diagram for pqfp package gnd nc rdy/dtack ct5 dt5 ct6 dt6 ct7 dt7 ct1 dt1 dt2 ct3 dt3 ct4 vdd cr19 dr20 cr24 dr25 gnd gnd dr24 p1 cr23 p0 gnd dt12 outdis dt8 ct8 ct2 dt4 cr20 dr23 dr21 gnd cr21 cr22 dr22 cr26 dr27 vdd dr26 cdcct cr25 hreset gnd gnd gnd dlen cr27 gnd nc cr28 cr17 dr17 cr16 dr16 cr15 dr15 dr14 cr13 cr12 dr12 cr11 dr11 dr10 cr9 dr9 cr4 dr4 m13x int/irq dr5 vdd cr5 dr28 dr18 cr18 dr19 gnd cr14 dr13 cr10 cr8 dr6 dr8 cr6 vdd dr7 cr7 a0 a1 dr2 cr2 dr3 cr3 nc gnd nc gnd a3 a2 gnd scan_en dt26 vdd ds3dt cckt cfmt xck cdt s6 s7 a/d0,d0 a/d1,d1 a/d2,d2 a/d3,d3 a/d5,d5 a/d6,d6 a/d7,d7 cdr cckr gnd gnd gnd dt27 ds3cr ct27 ct25 dt25 ct26 s5 vdd gnd a/d4,d4 vdd ds3dr sel gnd ale rd / rd/wr wr a7 a6 cdccr cr1 dr1 cfmr mtest gnd gnd gnd a4 a5 gnd nc tdo gnd dt11 txfrm ct11 dt10 ct10 vdd dt16 dt15 ct15 dt14 ct14 ct13 dt20 ct20 dt24 ct24 scan_shift gnd ct17 trs dt17 tck ct12 tms tdi ct9 dt9 ct16 dt13 dt19 ct18 vdd dt18 ds3ct ct19 gnd dt21 ct21 ct22 dt22 ct23 dt23 nc gnd nc ct28 dt28 gnd 35 55 50 45 40 5 125 130 135 140 145 150 155 10 15 20 25 30 1 75 70 80 120 115 110 105 100 95 90 85 65 60 200 180 185 175 160 165 170 190 195 205 lead diagram m13x TXC-03305aipq note: this a top view of the m13x 208-lead plastic quad flat package. some lead symbols may be abbreviated. see figure 28 for package dimension information. www.datasheet.in - 10 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet lead descriptions all ttl8ma i/os are slew rate controlled except for the ds3dt and ds3ct outputs. power supply, ground, and no connect notes for lead descriptions tables: * i = input; o = output; p = power ** see input, output and input//output parameters section below for type definitions. symbol lead no. bga lead no. pqfp i/o/p* type** name/function vdd c1, c4, d8, g16, k1, k14, p8, r11, r13 5, 32, 75, 88, 94, 126, 138, 183, 200 p vdd: +5-volt supply voltage, 5%. gnd a1, a13, c14, d14, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, p3, p15, r6 1, 18, 49, 52, 53, 55, 56, 67, 70, 84, 101, 102, 104, 105, 110, 124, 146, 153, 156, 157, 159, 160, 166, 191, 205, 206, 208 p ground: 0 volts reference. nc a2, d11, f4, f13, g15, k3, k15, n6, r7, t2, t7 2, 50, 51, 106, 107, 155, 158 -- no connect: nc leads are not to be connected, not even to another nc lead, but must be left float- ing. connection of nc leads may impair perfor- mance or cause damage to the device. if future revisions of the device are made, then these leads may have functions associated with them. www.datasheet.in - 11 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet ds1 receive interfaces symbol lead no. bga lead no. pqfp i/o/p type name/function cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 cr16 cr17 cr18 cr19 cr20 cr21 cr22 cr23 cr24 cr25 cr26 cr27 cr28 n4 n2 n3 m1 m4 l1 l4 j2 j3 h4 h1 g4 g1 f3 f2 e3 e2 d1 c8 b8 c7 b7 c6 b6 c5 a4 a3 d2 62 43 41 39 37 35 33 30 28 26 24 22 20 17 15 13 11 9 184 186 188 190 193 195 197 201 203 7 o ttl2ma receive ds1 clocks, channels 1 - 28: receive data is clocked out of the m13x on rising edges of these clocks. the clock for the first ds1 channel corresponds to cr1, while the clock for the last ds1 channel corresponds to cr28. during normal operation, the ds1 clock signals are derived from the ds3 clock signal (ds3cr) and are stretched due to overhead and stuff bit removal. when the m13x lead is tied low and the djb control bit is set to a 1, the internal djb circuits will be enabled, which will reduce the amount that these clocks are stretched, thereby reducing their jitter. during cer- tain ds3 alarm conditions (programmable via 1tais1 and 1tais0, bits 5 and 4 in register 20h) the m13x provides a ds1 clock signal for clocking out ais which is derived from the xck clock lead. www.datasheet.in - 12 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet dr1 dr2 dr3 dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 r5 p1 n1 m2 m3 l2 l3 k4 j1 j4 h3 h2 g3 g2 f1 e4 e1 d4 d3 a8 d7 a7 d6 a6 d5 b5 b4 c2 63 44 42 40 38 36 34 31 29 27 25 23 21 19 16 14 12 10 8 185 187 189 192 194 196 199 202 6 o ttl2ma receive ds1 data, channels 1 - 28: demulti- plexed ds1 channels. the first ds1 channel corre- sponds to dr1, while the last ds1 channel corresponds to dr28. during normal operation these data outputs are stretched due to overhead and stuff bit removal. when the m 13x lead is tied low and the djb bit is set to a 1, the internal djb circuits will be enabled, which will reduce the amount that these data outputs are stretched, thereby reducing their jitter. symbol lead no. bga lead no. pqfp i/o/p type name/function www.datasheet.in - 13 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet ds1 transmit interfaces symbol lead no. bga lead no. pqfp i/o/p type name/function ct1 ct2 ct3 ct4 ct5 ct6 ct7 ct8 ct9 ct10 ct11 ct12 ct13 ct14 ct15 ct16 ct17 ct18 ct19 ct20 ct21 ct22 ct23 ct24 ct25 ct26 ct27 ct28 b10 c10 a9 c9 d13 a12 d12 a11 f14 f15 e14 d15 j14 h13 h16 g13 m13 l16 l13 j15 p16 n14 n13 m16 t13 r14 t16 p14 175 177 179 181 167 169 171 173 139 141 143 147 130 132 134 136 119 121 123 128 111 113 115 117 95 97 99 108 i ttl transmit ds1 clocks, channels 1 - 28: tr a n s m i t data is clocked into the m13x on either the rising or falling edges of these clocks, depending on the set- ting of the invck bit. the clock for the first ds1 channel corresponds to ct1, while the clock for the last ds1 channel corresponds to ct28. www.datasheet.in - 14 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet dt1 dt2 dt3 dt4 dt5 dt6 dt7 dt8 dt9 dt10 dt11 dt12 dt13 dt14 dt15 dt16 dt17 dt18 dt19 dt20 dt21 dt22 dt23 dt24 dt25 dt26 dt27 dt28 a10 d10 b9 d9 b12 c12 b11 c11 f16 e13 e15 c13 j13 h14 h15 g14 l15 l14 k13 j16 n15 n16 m15 m14 t14 t15 r15 r16 176 178 180 182 168 170 172 174 140 142 145 165 131 133 135 137 120 122 127 129 112 114 116 118 96 98 100 109 i ttl transmit ds1 data, channels 1 - 28: the first ds1 channel corresponds to dt1, while the last ds1 channel corresponds to dt28. symbol lead no. bga lead no. pqfp i/o/p type name/function www.datasheet.in - 15 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet ds3 interface notes: 1. ds3ct is not slew rate limited. 2. ds3dt is not slew rate limited. symbol lead no. bga lead no. pqfp i/o/p type name/function ds3cr t6 68 i cmos ds3 receive clock: a 44.736 mhz clock that is used to clock ds3 data into the m13x. this clock is used as the time base for demultiplexing the ds3 data. when the loop timing feature is active (a 1 written into bit 3 (lptime) in 02h), or when the ds3 external transmit clock (xck) fails, this clock becomes the transmit clock. ds3dr p6 69 i cmos ds3 receive data: receive 44.736 mbit/s data is clocked into the m13x on rising edges of the receive clock (ds3cr). ds3ct k16 125 o ttl8ma 1 ds3 transmit clock: a 44.736 mhz clock which is derived from the external transmit clock input signal (xck) or from the ds3 receive clock (ds3cr) when loop timing mode is enabled or when the xck clock fails. it is used to clock ds3 data from the m13x. ds3dt p13 93 o ttl8ma 2 ds3 transmit data: transmit c-bit parity or m13 formatted ds3 data is clocked out of the m13x on rising edges of the transmit clock (ds3ct). txfrm e16 144 i ttlp transmit ds3 frame synchronization pulse: an active low pulse that is sampled on the rising edge of the transmit ds3 clock (xck or ds3cr), and is used to align the transmit ds3 frame. the x1 bit of the transmit ds3 frame is three clocks delayed with respect to the txfrm. the use of this lead is optional. if it is not used then it must either be left floating or pulled high. www.datasheet.in - 16 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet microprocessor interface symbol lead no. bga lead no. pqfp i/o/p type name/function p1 p0 a15 b14 161 162 i ttlp microprocessor interface type select: the type of microprocessor interface selected by these two bits is given in the table below: the multiplexed interface consists of eight bidirec- tional address/data leads, select, address latch enable, read, write and interrupt request. when p(1- 0) = h,h only address range 00h-1fh is accessible, address straps s5-s7 are active, and the m13x lead must be left floating or tied high. this enables back- wards compatibility of the 208-lead pqfp packaged devices with the predecessor m13e device that has the same package and lead assignments. it also enables functional compatibility with the earlier m13 device, which has a 160-lead pqfp package. when p(1-0) = h,l only address range 00h-3fh is acces- sible, address straps s6-s7 are active and the state of the m 13x lead determines whether the m13x func- tionality in registers 25h-3fh is enabled or disabled. the intel compatible interface (80x86 family) consists of eight address leads, eight bidirectional data leads, select, read, write, ready and interrupt request. the motorola compatible interface (680x0 family) con- sists of eight address leads, eight bidirectional data leads, select, read/write, data transfer acknowledge and interrupt request. for both the intel and motorola compatible interfaces, registers 00h-24h are accessible if m13x is high and registers 00h-3fh are accessible if m13x is low. address straps s6-s7 are active. p1 p0 interface high high multiplexed (only allowed when m13x lead is high) high low multiplexed low low intel compatible low high motorola compatible www.datasheet.in - 17 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet s7 s6 s5 n11, p11, t11 85, 86, 87 i ttlp address straps: when the intel, motorola, or multi- plexed ( p1 is high and p0 is low) microprocessor interfaces are selected, the two address straps, s7 and s6, allow the m13x to be partitioned as a seg- ment of memory. the straps define the address offset of the device. the address register is partitioned as shown below. the data register pointed to by the 6 least significant bits is only accessed if the 2 most sig- nificant bits match the address straps. address register partition for intel, motorola, or multi- plexed ( p1 is high and p0 is low) microprocessor interfaces: when the multiplexed microprocessor interface is selected, by setting p1 high and p0 high, the three address straps, s7, s6, and s5, allow the m13x to be partitioned as a segment of memory. the straps define the offset of the device. the address register is partitioned as shown below. the data register pointed to by the five least significant bits is only accessed if the three most significant bits match the address straps. address register partition for the multiplexed micropro- cessor interface when p1 is high and p0 is high: a7 a6 a5 a4 a3 a2 a1 a0 p4 r4 t3 r3 r2 t1 r1 p2 60 59 58 57 48 47 46 45 i ttlp address bus (intel/motorola): multiplexed - these leads are disabled when the multi- plexed interface is selected. intel/motorola - these are active high address line inputs that are used by the microprocessor for access- ing the m13x registers for a read/write cycle. a7 is the most significant bit. a/d7 d7 a/d6 d6 a/d5 d5 a/d4 d4 a/d3 d3 a/d2 d2 a/d1 d1 a/d0 d0 n8 n9 p9 t9 r9 n10 p10 t10 76 77 78 79 80 81 82 83 i/o ttl8ma address/data bus (multiplexed) or data bus (intel/ motorola): multiplexed - these bidirectional leads constitute address/data buses for accessing the m13x registers. intel/motorola - these bidirectional leads are used only for transferring data. the most significant bit is a/d7 or d7. symbol lead no. bga lead no. pqfp i/o/p type name/function m13x address register address bit 7 6 m13x address register address bit 7 6 5 www.datasheet.in - 18 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet sel t8 74 i ttl select: a low enables data transfers between the microprocessor and the m13x registers during a read/ write bus cycle. rd rd/wr p7 71 i ttl read (intel/multiplexed) or read/write (motorola): intel/multiplexed - an active low signal generated by the microprocessor for reading the m13x register locations. motorola - an active high signal generated by the microprocessor for reading the m13x register loca- tions. an active low signal is used to write to the m13x register locations. ale r8 73 i ttl address latch enable (multiplexed): multiplexed - an active high enable signal generated by the microprocessor. the falling edge is used to store an address during a read/write bus cycle. intel/motorola - not used. this lead should be tied low when not used. wr n7 72 i ttl write (intel/multiplexed): intel/multiplexed - an active low signal generated by the microprocessor for writing to the m13x register locations. motorola - not used. this lead should be tied high when not used. rdy/ dtack a14 163 o ttl8ma ready (intel) or data transfer acknowledge (motorola): intel/multiplexed - this output lead is not used, and it is always high when the sel lead is low, otherwise it is tri-stated. connection to an intel microprocessor is optional. if connected, a pull-up resistor is required. motorola - during a read bus cycle, a low signal indi- cates the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the accep- tance of data. a pull-up resistor is required for this lead. int/irq b1 4 o ttl8ma interrupt request: this is a tri-state interrupt request lead. this lead is tri-stated when not being driven active. when this lead is driven active, the ipolal bit (bit 6 in register 3dh) determines the polarity of this lead. this lead will be driven active when an interrupt request bit and its corresponding interrupt request mask bit are both set to a 1. an external pull-up or pull-down resistor is required to pull this lead to the proper inactive level when it is not being driven. symbol lead no. bga lead no. pqfp i/o/p type name/function www.datasheet.in - 19 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet receive c-bit interface symbol lead no. bga lead no. pqfp i/o/p type name/function cckr p5 65 o ttl8ma receive c-bit clock: a gapped clock signal is pro- vided for clocking out the selected receive c-bit data. data (cdr) is clocked out on the rising edges of cckr. cdr n5 66 o ttl8ma receive c-bit data: the following c-bits are pro- vided at this interface: c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. cfmr t5 64 o ttl8ma receive c-bit framing pulse: this positive fram- ing pulse occurs prior to the c2 bit. cdccr t4 61 o ttl8ma receive data link indication: a positive pulse that identifies the location of the three data link c- bits (c13, c14, and c15). the receive c-bit clock (cckr) may be and-gated with this signal to pro- vide a gapped data link clock signal for loading the three c-bits from the c-bit data (cdr) into external circuitry, such as in m13e device applications. this signal is not needed if the internal hdlc controller is used since the c13, c14, and c15 c-bits are then processed internally. this signal is enabled by placing a high on the dlen input signal lead. www.datasheet.in - 20 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet transmit c-bit interface symbol lead no. bga lead no. pqfp i/o/p type name/function cckt r12 92 o ttl8ma transmit c-bit clock: a gapped clock signal is provided for clocking in selected transmit c-bit data (cdt). data is clocked into the m13x on the rising edges of cckt. cdt n12 89 i ttl transmit c-bit data: the transmit gapped clock (cckt) is provided for clocking in the following c- bits: c2, c3 (depending on the setting of bit 7 of register 19h, c3clki), c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. an unused c- bit should be transmitted as a 1. c13, c14, and c15 are sourced by the transmit pmdl controller when it is enabled, even though the clock pulses for c13, c14, and c15 are still present. cfmt t12 91 o ttl8ma transmit c-bit framing pulse: this positive fram- ing pulse occurs prior to the c2 bit. cdcct a5 198 o ttl8ma transmit data link indication: a positive pulse that identifies the location of the three data link c- bits (c13, c14, and c15). the transmit c-bit clock (cckt) may be and-gated with this signal to pro- vide a gapped data link clock signal for pmdl appli- cations where it is desired to use an external hdlc controller instead of the on-chip hdlc controller, such as in existing m13e device applications. this signal is not needed if the internal hdlc controller is used. this signal is enabled by placing a high on the dlen input signal lead. www.datasheet.in - 21 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet control leads external clock symbol lead no. bga lead no. pqfp i/o/p type name/function outdis b13 164 i ttlp outputs disable: a low causes all m13x outputs and bidi- rectional signal leads to be set to a high impedance state for test purposes except the tdo, cdccr and cdcct leads. the cdccr and cdcct leads can be tri-stated by apply- ing a low to the dlen lead. this lead is provided with an internal pull-up resistor. dlen b3 204 i ttlp data link enable: normally left open. a high enables the transmit and receive data link indication signals, cdcct and cdccr. the data link indication signals identify the location of the three data link c-bits (c13, c14, and c15). this lead is provided with an internal pull-up resistor. hreset b2 207 i ttlp asynchronous device reset: this active low lead should be toggled low for a minimum of 25 ns and then high after the power to the m13x has stabilized, to perform a global reset of the m13x device. when a global reset occurs, the memory map is initialized to all 0s except for the xt and t2x1-t2x7 bits which are set to 1s, and internal circuitry is reset. this lead is provided with an internal pull-up resistor. m13x c3 3 i ttlp enable m13x functions: when this input lead is high, the m13x device has the same functionality as the m13e device. also, the txfrm lead and id bit can be used as well. all m13x functions in registers 25h-3fh are disabled and all counters are 8 bits long. when this lead is low, the m13x functions in registers 25h-3fh are enabled (i.e., all features of the device can be used), and all counters become 16 bits long. this lead is provided with an internal pull-up resistor. when the m13x lead is low, the new bit in register 1dh does not become set to one again after it is cleared when a continuous constant feac message is received. symbol lead no. bga lead no. pqfp i/o/p type name/function xck p12 90 i cmos external transmit clock: an external clock having a fre- quency of 44.736 mhz and a stability of 20 ppm is required to meet dsx-3 cross-connect requirements. the clock duty cycle should be kept to (50 5)%. the transmit clock is also used to operate the m13x microprocessor interface. the m13x monitors this clock for transitions. when a clock failure is detected, the m13x automatically switches to the receive clock (ds3cr) for multiplexer and microprocessor operation. receive loop timing (a 1 written to bit 3, lptime, in 02h) also causes the receive clock to become the transmit clock. www.datasheet.in - 22 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet test access port scan test leads symbol lead no. bga lead no. pqfp i/o/p type name/function tms d16 148 i ttlp test mode select: the signal present on this lead is used to control boundary scan test operations. this lead is provided with an internal pull-up resistor. tdi c16 149 i ttlp test data input: serial data input for boundary scan test messages. this lead is provided with an internal pull-up resistor. tdo c15 150 o ttl8ma test data output: serial data output whose infor- mation is clocked out on falling edges of tck. tck b16 151 i ttlp test clock: the input clock for boundary scan test- ing. the tdi and tms states are clocked in on its ris- ing edges. this lead is provided with an internal pull- up resistor. trs a16 152 i ttlp test reset: when an active low signal is applied to this lead, the m13x test access port (tap) controller resets and the boundary scan is disabled. the con- troller is also reset by holding the tms signal lead high for at least five rising clock edges of tck. dur- ing power-up of the m13x, this lead must be held low, to reset the tap controller. failure to do so may cause the tap controller to take control of the m13x output leads. when the boundary scan feature is not used, this lead must be tied low. the software reset function in register 1fh does not affect the boundary scan logic. this lead is provided with an internal pull- up resistor. symbol lead no. bga lead no. pqfp i/o/p type name/function mtest k2 54 i ttlp scan test: leave disconnected. scan_en r10 103 i ttlp scan test: leave disconnected. scan_shift b15 154 i ttlp scan test: leave disconnected. www.datasheet.in - 23 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883d, method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +6.0 v note 1 dc input voltage v in -0.3 v dd + 0.3 v note 1 storage temperature range t s -55 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow component temperature x time ti 270 x 5 o c x s note 1 moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 latch-up lu meets jedec jc-40.2 parameter min typ max unit test conditions thermal resistance - junction to ambient of pbga package. 38 o c/w 0 ft/min linear airflow thermal resistance - junction to ambient of pqfp package. 26 o c/w 0 ft/min linear airflow parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v i dd 150.5 ma p dd 790 mw inputs switching and worst case process and loading. www.datasheet.in - 24 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet input, output and input/output parameters all rise times are measured from 0 to 1.4v and all fall times are measured from v dd to 1.4v. input parameters for cmos input parameters for ttl input parameters for ttlp note: the ttlp input has a 50k ? (nominal) internal pull-up resistor. parameter min typ max unit test conditions v ih 0.7 x v dd v4.75 < v dd < 5.25 v il 0.3 x v dd v4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25; input = 0 to 5.25v input capacitance 4 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25; input = 0 to 5.25v input capacitance 4 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -0.1 -0.35 ma v dd = 5.25; input = 0 v input capacitance 4 pf www.datasheet.in - 25 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet output parameters for ttl2ma input/output parameters for ttl8ma notes: 1. this parameter only applies to ds3ct and ds3dt. 2. this parameter applies to all ttl8ma i/os except for ds3ct and ds3dt. parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 2.0 i ol 2.0 ma i oh -1.0 ma t rise 4.6 ns c load = 15 pf t fa l l 4.3 ns c load = 15 pf tri-state leakage current 10 av dd = 5.25 parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25; input = 0 to 5.25v input capacitance 5.5 pf v oh 2.4 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise (note 1) 2.4 ns c load = 25 pf t fa l l (note 1) 2.4 ns c load = 25 pf t rise (note 2) 2.7 ns c load = 25 pf t fa l l (note 2) 2.7 ns c load = 25 pf tri-state leakage current 10 av dd = 5.25 www.datasheet.in - 26 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet timing characteristics detailed timing diagrams for the m13x are illustrated in the figures 5 through 18 below with values of the tim- ing intervals tabulated below each waveform diagram. all output times are measured with a maximum of 15 pf load capacitance for ttl 2 ma outputs and 25 pf load capacitance for ttl 8 ma outputs. timing parameters are measured at voltage levels of v dd /2 for cmos input signals or 1.4 v for all ttl input and output signals. figure 5. ds3 receive timing parameter symbol min typ max unit ds3cr clock period t cyc 20.0 22.35 ns ds3cr duty cycle (t pwh /t cyc ) -- 405060% ds3dr setup time before ds3cr t su -1.0 ns ds3dr hold time after ds3cr t h 6.0 ns ds3cr ds3dr t cyc t h t su t pwh (input) (input) www.datasheet.in - 27 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 6. ds3 transmit timing parameter symbol min typ max unit xck/ds3cr or ds3ct clock period t cyc 20 22.35 ns xck/ds3cr or ds3ct duty cycle (t pwh /t cyc )-- 455055% ds3dt output delay after ds3ct t od(1) 2.0 8.0 ns ds3ct output delay after xck/ds3cr t od(2) 5.0 17 ns txfrm setup time before xck/ds3cr t su 1.0 ns txfrm hold time after xck/ds3cr t h 1.2 ns xck/ds3cr txfrm t cyc t pwh t h t su ds3ct ds3dt t cyc t od(1) t pwh t od(2) x1 (see note) note: txfrm is sampled by xck or ds3cr, whichever is the current transmit clock. the x1 bit of ds3dt is three (3) clock cycles (of xck/ds3cr) delayed with respect to txfrm . (input) (output) (output) (output) www.datasheet.in - 28 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 7. ds1 receive timing with djbs disabled figure 8. ds1 receive timing with djbs enabled note: when the djbs are enabled, the ds1 receive timing is derived from the transmit clock source, which can be ds3cr or xck. parameter symbol min typ max unit crn clock period t cyc 28 ds3cr cycles 64 ds3cr cycles ns crn high time t pwh 14 ds3cr cycles 50 ds3cr cycles ns crn low time t pwl 14 ds3cr cycles 22 ds3cr cycles ns drn output delay after cr t od -12 10 ns parameter symbol min typ max unit crn clock period t cyc 28 ds3cr/xck cycles 29 ds3cr/xck cycles ns crn high time t pwh 14 ds3cr/xck cycles 15 ds3cr/xck cycles ns crn low time t pwl 14 ds3cr/xck cycles 14 ds3cr/xck cycles ns drn output delay after cr t od -12 10 ns gap due to destuffing crn drn t od t cyc t pwh t pwl (output) (output) crn drn t od t cyc t pwh t pwl (output) (output) www.datasheet.in - 29 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 9. ds1 transmit timing notes: 1. each ds1 input can be asynchronous with respect to another ds1 channel. 2. the diagram above is shown for invck = 0. when invck = 1, the dtn signals are clocked into the m13x on the falling edges of their corresponding ctn signals. 3. the timing parameters in the table above do not change when invck = 1 except that t su and t h are measured with respect to the falling edges of the ctn signals. 4. the transmit ds1 inputs can accept jitter which exceeds the ds1 input jitter tolerance curve of gr- 499-core for category i interface. 5. ctn clock period max indicates the ability of the device to accept a gapped clock but does not indicate a continuous period. parameter symbol min typ max unit ctn clock period t cyc 583 648 1305 ns ctn high time t pwh 145 324 -- ns ctn low time t pwl 145 324 -- ns dtn setup time before ct t su 4.0 ns dtn hold time after ct t h 6.0 ns ctn dtn t cyc t pwh t h t su t pwl (input) (input) www.datasheet.in - 30 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 10. c-bit receive interface timing parameter symbol min typ max unit cckr clock period t cyc 3800 ns cckr output delay after cfmr t od(1) 3800 ns cdr output delay after cckr t od(2) 0.5 1.0 1.5 ds3cr/ xck clock cycle cckr delay after cdccr t d(1) 1900 ns cdccr delay after cckr t d(2) 3800 ns cfmr pulse width (high) t pw 1900 ns c2 c3 c4 c5 c6 c13 c14 c15 c16 c17 c18 c19 c20 c21 t od(1) t pw t cyc t d(2) cdr cckr cdccr cfmr t d(1) t od(2) (output) (output) (output) (output) www.datasheet.in - 31 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 11. c-bit transmit interface timing notes: 1. a c-bit must be transmitted as a 1 when not needed. 2. following normal power-up procedures, bit 7 in register 19h will be set to ? 0 ? and the extra clock pulse for the c3 bit in the cckt clock will be present. if bit 7 is then set to ? 1, ? the extra c3 bit clock pulse will not be present. parameter symbol min typ max unit cckt clock period t cyc 3800 ns cdt setup time before cckt t su 25 ns cdt hold time after cckt t h 40 ns cckt output delay after cfmt t od 3800 ns cckt delay after cdcct t d(1) 1900 ns cdcct delay after cckt t d(2) 3800 ns cfmt pulse width t pw 1900 ns c2 c4 c5 c6 c13 c14 c15 c16 c17 c18 c19 c20 c21 t pw t cyc t d(2) cdt cckt cdcct cfmt t d(1) (output) (input) (output) (output) t su t h t od c3 www.datasheet.in - 32 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 12. microprocessor read cycle timing - multiplexed interface notes: 1. the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the rdy/dtack output lead is always driven high when the sel lead is low, otherwise it is tri-stated, which corresponds to the behavior of the m13e device. 2. the sel lead must be brought high for 2 transmit clock cycles before the start of a new read cycle. parameter symbol min typ max unit ale pulse width t pw(1) 95 ns ale wait after rd t w(1) 20 ns a/d(7-0) address setup time before ale t su 30 ns a/d(7-0) address hold time after ale t h(1) 25 ns a/d(7-0) address hold time after rd t h(2) 20 ns a/d(7-0) data output delay (to tri-state) after rd t od(1) 10 50 ns a/d(7-0) data valid delay after rd t od(2) 150 ns sel wait after ale t od(3) 80 ns rd pulse width t pw(2) 180 212,000 ns rd wait after ale t w(2) 25 ns t pw(1) t su t w(1) t h(1) t w(2) t od(3) t pw(2) t od(2) ale a/d(7-0) sel rd t h(2) t od(1) address data www.datasheet.in - 33 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 13. microprocessor write cycle timing - multiplexed interface notes: 1. the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the rdy/dtack output lead is always driven high when the sel lead is low, otherwise it is tri-stated, which corresponds to the behavior of the m13e device. 2. the sel lead must be brought high for 2 transmit clock cycles before the start of a new write cycle. parameter symbol min typ max unit ale pulse width t pw(1) 95 ns ale wait after wr t w(1) 20 ns a/d(7-0) address setup time before ale t su 30 ns a/d(7-0) address hold time after ale t h(1) 25 ns a/d(7-0) data hold time after wr t h(2) 20 ns sel wait after ale t od 80 ns wr pulse width t pw(2) 200 212,000 ns wr wait after ale t w(2) 25 ns t pw(1) t su t w(1) t h(1) t w(2) t od ale a/d(7-0) sel wr t h(2) t pw(2) address data www.datasheet.in - 34 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 14. microprocessor read cycle timing - intel interface notes: 1. the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the rdy/dtack output lead is always driven high when the sel lead is low, otherwise it is tri-stated, which corresponds to the behavior of the m13e device. 2. the sel lead must be brought high for 2 transmit clock cycles before the start of a new read cycle. parameter symbol min typ max unit a(7-0) address hold time after rd t h(1) 0.0 ns a(7-0) address setup time before s el t su(1) 20 ns d(7-0) data valid delay after rd t d 60 ns d(7-0) data float time after rd t f 80 ns rd pulse width t pw 80 212,000 ns sel setup time before r d t su(2) 10 ns sel hold time after rd t h(2) 0.0 ns d(7-0) sel rd t h(2) t f t su(2) t su(1) t pw t h(1) a(7-0) t d www.datasheet.in - 35 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 15. microprocessor write cycle timing - intel interface notes: 1. the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the rdy/dtack output lead is always driven high when the sel lead is low, otherwise it is tri-stated, which corresponds to the behavior of the m13e device. 2. the sel lead must be brought high for 2 transmit clock cycles before the start of a new write cycle. parameter symbol min typ max unit a(7-0) address hold time after wr t h(1) 0.0 ns a(7-0) address setup time before s el t su(1) 20 ns d(7-0) data valid setup time before w r t su(2) 20 ns d(7-0) data hold time after wr t h(2) 5ns sel setup time before w r t su(3) 10 ns wr pulse width t pw 80 212,000 ns d(7-0) sel wr t h(2) t su(1) t su(3) t pw t su(2) t h(1) a(7-0) www.datasheet.in - 36 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 16. microprocessor read cycle timing - motorola interface note: the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the dtack signal lead has the same functional timing as the m13e device when the m13x lead is high. parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 0.0 ns a(7-0) address valid setup time before s el t su(1) 20 ns d(7-0) data valid delay after dtack t d(1) 16 21 ns d(7-0) data hold time after sel t h(2) 42 ns sel pulse width t pw(1) 60 212,000 ns rd/wr setup time before s el t su(2) 20 ns rd/wr hold time after sel t h(3) 0.0 ns dtack delay after sel t d(2) 60 ns dtack pulse width t pw(2) 0.0 100 ns dtack float time after sel t f 20 ns d(7-0) sel rd / wr dtack t f t h(2) t d(1) t pw(2) t su(2) t su(1) t pw(1) t d(2) t h(1) t h(3) a(7-0) note: the dtack signal lead is tri-stated when sel is high. (see note) www.datasheet.in - 37 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 17. microprocessor write cycle timing - motorola interface note: the transmit clock (xck) or receive clock (ds3cr) must be present for the microprocessor bus interface to operate. the dtack signal lead has the same functional timing as the m13e device when the m13x lead is high. parameter symbol min typ max unit a(7-0) address hold time after sel t h(1) 0.0 ns a(7-0) address valid setup time before s el t su(1) 20 ns d(7-0) data valid setup time before s el t su(2) 10 ns d(7-0) data hold time after sel t h(2) 5.0 ns sel pulse width t pw(1) 60 212,000 ns rd/wr setup time before s el t su(3) 20 ns rd/wr hold time after sel t h(3) 0.0 ns dtack delay after sel t d 60 ns dtack pulse width t pw(2) 100 ns dtack float time after sel t f 20 ns d(7-0) sel rd / wr t f t pw(2) t su(1) t su(3) dtack t su(2) t h(2) t pw(1) t d t h(1) t h(3) a(7-0) note: the dtack signal lead is tri-stated when sel is high. (see note) www.datasheet.in - 38 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 18. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time before tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time before tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 3.0 - ns tdo delay from tck t d -10ns trs pulse width t pw 100 - ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl trs (input) t pw www.datasheet.in - 39 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet operation the sections below contain descriptions of the m13x features. in the m13x device, the counters, interrupt request bits, interrupt mask bits, new control bits, and pmdl fifo interface will be located at addresses 25h- 3fh. m13x lead in order to maintain backwards compatibility with the m13e device, a control lead with an internal pull-up, m13x , has been added. when this lead is set to high, or left floating, all of the m13x functions contained in address locations 25h-3fh are disabled. this means that: the pmdl (path maintenance data link) c-bits are inserted and extracted solely through the exter- nal c-bit interfaces (in c-bit parity format mode) or by the internal stuffing logic (in m13 format mode). the internal dejitter buffers (djbs) are bypassed. the external address straps s5-s7 operate as in the m13e device. only the registers defined by the settings of the p0 and p1 leads and straps s5-s7 are accessible. any reads from addresses outside of those ranges cause the microprocessor interface of the m13x to remain tri-stated. any writes to locations 25h-3fh will not have any effect on device operation. fur- thermore, when the p0 and p1 leads are both set to high, registers 20h-3fh are not accessible for read or write operations. all counters are 8 bits long, clear when read, and saturate when a count of ffh is reached. the txfrm lead is operational. new bit will be set under the conditions that caused the new bit to be set in the m13e device. namely, the new bit becomes set when any five consecutive and identical feac messages are received. the new bit will continually be reasserted if it is read and cleared when a continuous con- stant feac message is received. when the m 13x lead is set to low: the bits in registers 25h-3fh can be used to control, enable/disable, and monitor the m13x func- tions. the address strap s5 is ignored. address straps s6 and s7 are enabled to allow the m13x to be mapped to address ranges 00h-3fh, 40h-7fh, 80h-bfh, or c0h-ffh. when the m13x is mapped to an address range, all accesses to addresses outside of that range are handled by the m13x as if the sel chip-select input lead is high. that is, all read operations cause the microprocessor bus to be tri-stated and write operations will not have any effect upon any register. furthermore, when lead p1 is high and p0 is low, the multiplexed mode of operation is selected, but access to all registers (00h-3fh) is provided. setting both p1 and p0 high is not allowed. the counters become 16 bits in length, clear when read, and saturate 1 when a count of ffffh is reached. when the low byte of a 16-bit counter is read, the high byte is simultaneously written to a common high byte register location (3eh). so, in order to read a 16-bit counter, the counter register is read first to get the low byte, then the common high byte register is read to get the high byte. the txfrm lead is operational. new bit in register 1dh does not become set to one again after it is cleared when a continuous con- stant feac message is received. regardless of the setting of the m13x lead, the m13xid0 bit (register 10h, bit 7) bit will always be set to 0. the 1. saturate, as used throughout this document when referring to a counter, means that a counter stops at its maximum count and does not roll over to zero when the next count event occurs. www.datasheet.in - 40 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet m13xid0 bit is used by external software to determine if the device being accessed contains an m13e or an m13x die. the end user would use this bit as follows before the device is configured: register 10h is written with 00h the end user verifies that 10h contains 00h register 10h is written with 80h the end user reads 10h again. if it is 00h, then the device contains an m13x die. if 80h is read back, then the device contains an m13e die. as an additional check to ensure that the microprocessor interface is working, the end user can verify that bit 7 of register 11h can be written with a 1 and a 0. this bit does not do anything in either device, it is just a read/write bit. resets an active low hardware reset signal lead, hreset , is provided to reset the m13x device from an external source. the operation of this lead is also asynchronous. when this lead is asserted low the following functions occur: reset registers 00h, 02h-14h, and 16h-3fh to 00h. reset register 01h to 01h. reset register 15h to 7fh. perform the same reset functions as the software reset of register 1fh. reset all of the device to a known state. please note that the hardware reset does not have any effect on the boundary scan tap controller. figure 19 shows the functional architecture of the resets in the m13x device. please note that this diagram rep- resents functionality and not necessarily implementation. figure 19. m13x reset structure software reset reset for system logic (active low) reset for tap controller (active low) hreset lead trs & software reset function of m13x device (active low) active low signal lead note: low corresponds to logic 0 in this diagram. www.datasheet.in - 41 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet integrated djb devices the dejitter buffer (djb) is a transwitch circuit design that takes in jittered ds1s from a ds3 to ds1 demux process and smooths out the ds1s. the m13x device contains 28 of these djbs. the option to bypass the djbs through a control bit, djb, is provided when the m13x lead is low. when m13x is high, the djbs are unconditionally bypassed. the djb control bit is located at bit 7 of register 3dh. when m13x is low the djb control bit operates as fol- lows: djb = 0. the djbs are bypassed. djb = 1. the djbs are enabled and the 28 receive ds1s are dejittered. the djbs are located in the m13x device such that when they are enabled (i.e., djb = 1 and m13x is low), the receive ds1 channels that are looped back are also dejittered. the xck signal is normally used to operate the djbs, therefore it needs to be stable and clean. in the event that the xck clock is lost (i.e., t3ckf = 1), the ds3cr clock is automatically substituted in place of the xck clock. each djb has an automatic self-reset function that allows individual djbs to be reset (i.e., only the djbs that need to be reset are reset, while the others operate normally) upon djb fifo underflow/overflow. however, when the 44.736 mhz reference clock to the m13x is switched from xck to ds3cr or vice versa, a manual reset via the software reset register can be performed via software control. the following conditions activate the djb reset: software reset activated hardware reset activated fifo overflow or underflow (in this case, the reset is performed automatically for the individual djb that has underflowed or overflowed) note that, when in loop timing mode (lptime = 1), the transmit clock (in this case the ds3cr signal) is used as the 44.736 mhz reference clock for the djbs. the ds3 reference clock frequency tolerance needs to be within 20 ppm inclusive. the ds1 signals that are embedded in the demuxed ds3 signal originated at a mux somewhere else in the system. the original frequency of these ds1s needs to be within 130 ppm of the nom- inal frequency. the m13x meets and exceeds the jitter requirements for all possible combinations of ds3 and ds1 clock off- sets indicated below: ds3 clock offset: +/- 20 ppm ([gr-499] table 9-16 line-rate accuracy parameter) tx ds1 clock offset: +/- 130 ppm ([gr-499] r9-64 section 9.3.2) rx ds1 clock offset: +/- 32 ppm ([gr-499] table 9-13 line-rate accuracy parameter). this parameter must always be met when the line rate of the channelized ds1 signal being demultiplexed is within +/ - 32 ppm. the m13x meets and exceeds the timing jitter requirements specified in [gr-499] for: tolerance ([gr-499] section 7.3.1) transfer ([gr-499] section 7.3.2) generation ([gr-499] section 7.3.3) enhancement ([gr-499] section 7.3.4) www.datasheet.in - 42 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet jitter tolerance input jitter tolerance is defined in [gr-499] section 7.3.1 as: "the minimum amplitude of sinusoidal jitter at a given frequency that, when modulating the signal at an equip- ment input port, results in more than 2 errored seconds in a 30-second measurement interval." in accordance with the above, the m13x was tested in all the channelized t1 signals during a 30-second mea- surement interval when the jitter mask indicated below was applied to the tx ds1 signals when the tx ds3 clock (xck or ds3cr) and the tx ds1 input clocks were varied over their line rate accuracy specified above. 1 this requirement was also met when loop timing mode was enabled and the maximum amount of tolerable jit- ter applied to the ds3cr signal (i.e. the tx clock). the m13x tolerated more jitter than is indicated in the gr- 499 mask requirements, as shown below. the m13x was tested in the t3 and channelized t1/t2 2 signals during a 30-second measurement interval when the jitter mask indicated below was applied to the rx ds3 signal when the rx ds3 clock (ds3cr) and the channelized ds1 input clocks were varied over their line rate accuracy specified above. the m13x toler- ated more jitter than is indicated in the gr-499 mask requirements, as shown in figures 20 and 21. 1. when verifying ds1 jitter tolerance, it is acceptable to loop back the ds3 signal and measure the errors that occur on the demultiplexed ds1 signals. the djbs should be enabled during such a test to ensure that they do not drop data. 2. it is sufficient to only check the rx ds1s for errors, however a more complete, but not required, check should include all of the signals. www.datasheet.in - 43 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 20. ds1 input jitter tolerance input jitter amplitude (uipp) jitter frequency (hz) 0.1 slope = -28.22 1.0 0.01 10 100 1,000 10,000 100,000 1.0 10 100 5 500 8,000 40,000 40 400 4000 ds1 jitter tolerance mask to gr-499-core db/decade jitter frequency (hz) input jitter amplitude (uipp) 10 18.564 40 9.814 100 7.314 400 6.064 1000 5.861 4000 2.423 10000 1.134 40000 0.556 measured for m13x www.datasheet.in - 44 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 21. ds3 input jitter tolerance jitter frequency (hz) 1.0 slope = -20 1.0 0.1 10 100 1,000 10,000 100,000 10 100 ds1 jitter tolerance mask to gr-499-core db/decade jitter frequency (hz) input jitter amplitude (uipp) 10 <64 100 <64 600 <64 1,000 <64 10,000 <64 30,000 59.438 100,000 17.139 400,000 2.374 1,000,000 669 22,300 300,000 600 30,000 400,000 0.3 measured for m13x www.datasheet.in - 45 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet jitter transfer jitter transfer requirements are defined in [gr-499] section 7.3.2 for ds3 to ds1 and also for ds1 to ds3 to ds1 interfaces. the jitter transfer functions listed below shall be met for all ds1 and ds3 frequency offsets, and djb reference clock offsets; the actual performance of the part at typical clock frequency offsets is super- imposed. the jitter transfer masks shown in figures 22 and 23 show the maximum allowable gain in the jitter over a specified range of frequencies going from one port to another. note: only at 15 khz, the m13x exceeds the jitter transfer mask limits; and that is because the generated jit- ter at those frequencies is high compared to the 0.3 ui input jitter applied. the generated jitter is well within the 1.0 ui spec at 15 khz. the gr-499-core section 7.3.2 states that at such frequencies, the jitter transfer can- not be measured. www.datasheet.in - 46 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 22. ds3 to ds1 interface jitter transfer limits input jitter amplitude (uipp) jitter frequency (hz) 0.1 slope = -20 1.0 -10 10 100 1,000 10,000 100,000 ds1 jitter transfer mask to gr-499-core db/decade jitter frequency (hz) jitter gain (db) 10 -25.11 100 -28.42 1,000 -45.18 14,000 -56.40 15,000 -46.07 2500 15,000 350 14,000 -20 -30 -40 -60 -34.05 -49.61 slope = -40 db/decade -50 0 measured for m13x exceeds measurement limits at 15,000 hz see note in ? jitter transfer ? section www.datasheet.in - 47 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 23. ds1 to ds1 jitter transfer limits jitter frequency (hz) jitter gain (db) 10 0.07 40 -8.16 100 -15.72 350 -27.42 1,000 -37.00 2,500 -44.71 15,000 -40.46 input jitter amplitude (uipp) jitter frequency (hz) 0.1 slope = -20 -10 ds1 jitter transfer mask to gr-499-core db/decade -20 -30 -40 -60 -34.05 -49.61 slope = -40 db/decade -50 0 10 1.0 10 100 1,000 10,000 100,000 2500 15,000 350 40 measured for m13x exceeds measurement limits at 15,000 hz see note in ? jitter transfer ? section www.datasheet.in - 48 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet jitter generation in the absence of input jitter on any clock applied to the m13x device, the jitter generated at the rx ds1 output (with the djb function enabled) shall be less than 0.3 uirms and also less than 1.0 uipp over the jitter frequen- cies of 10 hz - 40 khz ([gr-499] r7-7 section 7.3.3 and table 7-1) and over all of the ds1 and ds3 clock off- sets. this requirement applies only to a multiplexer demultiplexer pair. jitter generation criteria for the ds3 interface is not defined at this time. as a goal, the jitter at the tx ds3 out- put of a arte/m13x pair is required to be less than 5 uipp over a jitter frequency range of 10hz - 400 khz and 0.1 uipp over a jitter frequency range of 30 khz - 400 khz. jitter enhancement the ds1 jitter output at an rx ds1 of the m13x is less than 5.0 uipp over a jitter frequency range of 10 khz - 40 khz, after that ds1 signal went through 12 (or more) m13x multiplexer/demultiplexer pairs. this require- ment is met when the 1st ds1 signal has 4.0 ui applied to it over a jitter frequency range of 10 hz - 350 hz. this requirement does not need to be met when the djbs are bypassed but must be met when they are enabled. also, no bit errors occur. residual jitter when the djbs are enabled and the demultiplexed ds1 signals do not have any jitter on them, the ds1 jitter output of the m13x is about 0.30 uipp and 0.038 uirms over a 10hz - 40 khz jitter frequency range and about 0.028 uipp and 0.014 uirms over an 8 khz - 40 khz jitter frequency range for all ds1 and ds3 clock offset fre- quencies. www.datasheet.in - 49 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet interrupts a set of interrupt request bits and corresponding mask bits is provided in the m13x. an interrupt request bit is a bit that latches to a 1 when a certain condition occurs and can cause an interrupt to be signaled on an exter- nal interrupt request lead (int/irq ) if the corresponding interrupt request mask bit is also set to a 1. an inter- rupt request bit will remain set to a 1 even when the condition that caused it to become set is removed. an interrupt request bit can be cleared by reading it. two control bits, rise and fall, are used to control the con- ditions for setting the non-pmdl related interrupt request bits. when rise = 1, the interrupt request bits are set on the entrance of an alarm/condition. when fall = 1, the interrupt request bits are set on the exit of an alarm/condition. when rise and fall are both set to 1, the interrupt request bits are set on both the entrance and exit of an alarm/condition. when rise and fall are both set to 0, the interrupt request bits are disabled. note that the rise and fall bits do not affect the pmdl interrupt request bits in register 2ch. these bits are significant only when set on the entrance of a condition and therefore only become set on the entrance of their corresponding condition. it is important to note that the interrupt request bits are set by their real-time counterparts, and not from other latched bits. for example, the interrupt request bit for the r3los alarm is not set by the latched r3los bit in register 16h but is set by the real-time r3los bit in register 00h. interrupts need to be serviced within a specific period of time after they are signaled by the int/irq lead. the table below indicates the time interval within which the interrupt request bits need to be read and processed. register address (hex) description 25 the irlbn and irlball bits should be accessed within 131 s. 26 the irlbn and irlbds3 bits should be accessed within 131 s. 27 the irlbn bits should be accessed within 131 s. 28 this register should be read within 7.6 s to ensure that the irsef bit is read before it can change. 29 this register should be read within 7.6 s to ensure that the ds3 status bits are read before they can change. 2a this register should be read within 26 s to ensure that the irds2oofn bits are read before they can change. 2b once a counter saturates, it must be read before the next count comes in to ensure that no counts are lost. the worst case condition would occur for the f and m bit error counters (reg- ister 04h in m13 format mode) and register 1bh. in this case this register and the ds3 f-bit and m-bit counter would need to be read within 1.9 s. since the m13x provides 16-bit wide counters (when m13x is low) the counters do not have to be read very often to ensure that they do not saturate. reading the 16-bit counters in the m13x once a second is sufficient to ensure that they will not saturate. 2c once an interrupt request from one of the pmdl controllers is received it is recommended that this register, the rx pmdl message length register (39h), the rx pmdl fifo depth register (3ah), and at least one byte from the rx pmdl fifo interface register (38h) are read within 212 s before they can be updated by the next pmdl byte. www.datasheet.in - 50 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet pmdl operation the terminal-to-terminal path maintenance data link (pmdl) is a 28.2 kbit/s channel, which is available in the c-bit parity format mode, and is used to communicate ds3 path identification, ds3 signal identification, and ds3 test signal identification between terminals. the pmdl channel is carried in the c13, c14, and c15 ds3 c-bits and uses an hdlc protocol as defined in itu-t recommendation q.921 (3/93). the hdlc message frame is composed of four parts: an opening flag, the message (which consists of 79 bytes), a two-byte fcs-16 frame check sequence, and a closing flag, as shown in 24 below. figure 24. hdlc format the bit numbering convention indicated in [q.921] sections 2.8.2 and 2.8.3 is followed in figure 24. the pmdl block (or hdlc controller) performs the following functions: zero bit stuffing/destuffing (11111 to 111110 /111110 to 11111) ([q.921] section 2.6) itu-t fcs-16 generation/checking (16-bit sequence) ([q.921] section 2.7) flag generation/detection (01111110) ([q.921] section 2.2) abort generation/detection (01111111...) ([q.921] section 2.10) start of frame detection ([q.921] section 2.2) end of frame detection ([q.921] section 2.2) fifo overflow and underflow invalid frame detection and discard ([q.921] section 2.9). bit 1 is the least significant bit and is the first bit transmitted/received. the opening and closing flags are repre- sented by a single, unique 8-bit character defined as 01111110, which contains six contiguous ones. a two- byte fcs-16 frame check sequence is computed across the contents of the message (after the opening flag), and appended to the end of the message. the polynomial for the fcs is x 16 +x 12 +x 5 +1 as specified in [q.921] section 2.7. to avoid the occurrence of a false flag within the transmit data stream, a 0 is inserted (stuffed) after each string of five contiguous ones between the opening and closing flags. the time between consecutive frames is filled with one or more flags. in the receive direction, the hdlc controller frames to the flag characters to determine the byte boundary and the start of the data. all flags are discarded and destuffing is performed on the data. destuffing is the process of replacing any 111110 patterns detected between the opening and closing flags with 11111. reception of more than six contiguous ones before destuffing is interpreted as a frame abort sequence. when an abort sequence is received, the remainder of the current frame is ignored and the received portion should be dis- carded by the end user as an invalid frame. when two or more frames occur in sequence, they may share the boundary flag between them (i.e., the closing flag of the first frame can serve as the opening flag of the next frame) ([q.921] section 2.2). the m13x is able to successfully delineate hdlc-encapsulated pmdl messages in this case. an 80-byte pmdl fifo is provided in the transmit direction to allow at least one complete message to be stored for processing. a 159-byte pmdl fifo is provided in the receive direction, which permits at least two bit87654321 opening flag01111110 message address and control information (79 bytes) fcs-16 2 8 2 15 2 0 2 7 closing flag01111110 www.datasheet.in - 51 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet ansi t1.107 lapd messages to be received. interrupts and status information are provided to facilitate fifo servicing by the microprocessor. the hdlc receiver is enabled when a 1 is written to control bit ehr (bit 4) in register 3dh. when enabled, the receive pmdl c-bits (c13, c14, and c15) are extracted from the receive ds3 stream. the flag sequence is checked to determine the byte boundary. after the octet boundary is established, the first non-flag octet signi- fies the start of the information field. at this point, the hdlc receiver will remove the stuffed 0 bits and place the message contents, aligned to octet boundaries, into the 159-byte receive pmdl fifo. it is important to note that the first bit received is the least significant bit and goes into bit location 0 1 of the octet. 2 the hdlc controller will check the fcs to ensure that it is correct. the received fcs is not stored in the fifo and is dis- carded after being checked. only the de-stuffed information between the opening and closing flags is written to the receive pmdl fifo. please note that receive pmdl fifo overflow does not necessarily result in an fcs error since the fcs is checked before data is written into the receive pmdl fifo. if the fcs check fails, then the rx fcs error counter at address 3bh increments and the irrhis(2-0) bits in register 2ch are set to 011 to signal that an fcs error has occurred. the rx fcs error counter is a read-only 16-bit counter that clears on read. fcs error counts are not lost during a read. if an abort sequence is detected (i.e., an octet that contains more than 6 consecutive 1s is detected), only the information field received up to that point is written to the receive pmdl fifo. furthermore, the rx abort counter at register 3ch increments, and the irrhis(2-0) bits in register 2ch are set to 100 to signal that an abort has occurred. the rx abort counter is a 16-bit read only counter that clears on read. abort counts are not lost during a read of this counter. the rx pmdl fifo depth and rx pmdl message length registers, at 3ah and 39h, are also updated accordingly, as described in the paragraphs below. the receive ds3 c-bit interface operation is not affected by the setting of the ehr control bit. when ehr = 0, the receive pmdl controller is disabled, and no interrupt requests are generated. the receive pmdl fifo is monitored for fill level, with maskable interrupts provided. bits irrxfs1 and irrxfs0 (bits 4 and 3) in register 2ch indicate when the receive pmdl fifo is equal to or greater than half full, full, and overflowed. an interrupt may also be activated at the end of the message, or when the fifo is half full, using the rhie control bit (bit 5) in register 3dh to control the conditions for which interrupt request bits irrhis(2-0) (bits 7 - 5) in register 2ch change. if it is desired to signal an interrupt at the end of a message, the rhie control bit can be set to 0. then the hdlc controller will generate an interrupt only on the completion of the message. if mask bits mirrhis(2-0) (bits 7 - 5 in register 35h) are set to 110, an interrupt will occur when irrhis(2-0) = x1x or 1xx; irrhis(2-0) will also hold the latched value. the controller will generate an interrupt when the fifo is half filled by setting rhie 3 = 1; mask bits mirrhis(2-0) should be set to 110, but now the interrupt based on irrhis(2-0) = 010 will occur both at the end of message and when the fifo reaches half full. this same function may be accomplished by leaving rhie = 0 and by monitoring the fifo fill level using status bits irrxfs1 and irrxfs0 to detect fifo fullness. to generate an interrupt from the irrxfs1 and irrxfs0 interrupt request bits, mask bits mirrxfs1 and mirrxfs0 (bits 4 and 3) in register 35h should be set to 11; when the receive pmdl fifo is equal to or more than half full, interrupt request bits irrxfs1 and irrxfs0 (bits 4 and 3) in register 2ch will be set to 01 and an interrupt will be generated. the rx pmdl fifo depth register at address 3ah provides the number of bytes presently stored in the receive fifo. bits irrhis(2-0) (bits 7-5 in register 2ch) provide message status and error indications. the receive pmdl controller will generate a maskable interrupt for start of message detected, valid message received, fcs in error, message aborted, and invalid frame received. the message bytes are read by the microprocessor from the rx pmdl fifo at register 38h. bit 0 corresponds to the first bit received in a byte. to accommodate back-to-back messages, a rx pmdl message length register is provided at address 39h, which is loaded with the length of the received message, in bytes, at the end of every message (valid 1. transwitch bit numbering format is used here. bits are ordered 7-0 (most significant bit - least significant bit). 2. caution: the first bit transmitted/received in the hdlc protocol is the least significant bit. see sections 2.8.1 and 2.8.2 in [q.921]. please also note that in [q.921] bits are numbered 8-1 (most significant bit-least significant bit) instead of 1-8 (most significant bit-least significant bit) as in some other documents. 3. this setting of rhie is used when the message is expected to be longer than 159 bytes. www.datasheet.in - 52 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet received, aborted, received with bad fcs, or an invalid frame was received). when an interrupt occurs indicat- ing a message has been received, the rx pmdl message length register should be read. the message length along with message status may be queued for processing later. the value in the rx pmdl fifo depth register is not reset at the end of a message. when initializing the hdlc controller, the receive pmdl fifo must be read repeatedly until the depth value in the rx pmdl fifo depth register is zero. it should be noted that messages with bad fcs or messages that were aborted must also be cleared from the receive pmdl fifo by the end user. invalid frames are detected and discarded. [q.921] section 2.9 identifies and defines six different situations that can be considered an invalid frame: a. a frame that is not properly bounded by two flags (i.e., a frame that violates a maximum or minimum length). the m13x will allow any length frame to be received, therefore it will be up to the end user ? s soft- ware to determine if the received frame is too long. b. there are fewer than 6 octets between flags of frames that contain sequence numbers and fewer than five octets between flags of frames that do not contain sequence numbers (for the case of the m13x, unnum- bered sequences are used, see figure 26 in [t1.107] and sections 3.4 and 3.4.3 in [q.921], therefore the 5 octet requirement applies to the m13x). c. the frame does not consist of an integral number of octets prior to bit insertion or following zero bit extrac- tion. d. the frame contains a frame check sequence error. e. the frame contains a single octet address field. f. the frame contains a service access point identifier ([q.921] section 3.3.3) which is not supported by the receiver. items a-f below indicate how the requirements in items a-f directly above are implemented in the m13x: a. no hardware support is provided for detecting if received frames are too long. the m13x can accept frames of any length. software can determine that the frame is too long and can read it out of the fifo and then chose to discard the data. b. when a frame contains 4 or fewer octets, after destuffing, between its opening and closing flags: the irrhis(2-0) interrupt request bits (bits 7-5 of register 2ch) are set to 111. the frame is written to the receive pmdl fifo. the rx pmdl fifo depth register indicates the correct depth of the receive pmdl fifo. the rx pmdl message length register indicates the correct message length. an fcs error is not counted or declared. c. when a receive 1 frame does not consist of an integral number of octets after the destuffing process: the irrhis(2-0) interrupt request bits (bits 7-5 of register 2ch) are set to 111. the frame is written to the receive pmdl fifo, except for the partial byte. the rx pmdl fifo depth register indicates the correct depth of the receive pmdl fifo. the rx pmdl message length register indicates the correct message length. an fcs error is not counted or declared. d. when a receive frame contains a frame check sequence error: the irrhis(2-0) interrupt request bits (bits 7-5 of register 2ch) are set to 011. 1. transmit frames in the m13x are exempt from checking, since the transmit pmdl data are written into the transmit pmdl fifo as octets. also, it is not expected that the transmit pmdl message stop transmitting on a non-octet boundary. therefore all transmit pmdl messages will default to an integral number of octets in length, before stuffing. www.datasheet.in - 53 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet the frame is written to the receive pmdl fifo. the rx pmdl fifo depth register indicates the correct depth of the receive pmdl fifo. the rx pmdl message length register indicates the correct message length. the rx fcs error counter increments by 1. e. no hardware support is provided for receive frames that have a single octet address field. this type of frame is handled as a normal frame. user software can determine that the frame has a single octet address field by reading it out of the fifo and then choose to discard the data. f. no hardware support is provided for receive frames that have an invalid service point access identifier. this type of frame is handled as a normal frame. software can determine that the frame has an invalid service point access identifier by reading it out of the fifo and then choose to discard the data. the transmit pmdl controller is disabled when a 0 is written to control bit eht (bit 0) in register 3dh or when a high is applied to the m13x lead or it is left floating. when disabled, the pmdl c-bits are sourced from either the external ds3 c-bit interface when m13mode = 0 (bit 0 register 02h) or from internal stuffing logic when m13mode = 1. the hdlc transmitter is enabled when a 1 is written to control bit eht while a low is applied to the m13x lead. when enabled, the transmit pmdl controller will transmit flags until data is placed in the trans- mit fifo. up to 80 bytes can be placed in the transmit pmdl fifo at once, but only 79 bytes are required. the message bytes must be written into the transmit pmdl fifo by writing into the tx pmdl fifo register at 37h. bit 0 corresponds to the first bit transmitted. the transmit bytes are read from the transmit pmdl fifo, a 16-bit fcs is computed until the end of message is detected, and zero insertion (stuffing) is performed over the mes- sage and fcs as needed. please note that the stuffing function is performed on all of the bytes between the opening and closing flags including the fcs. the fcs is calculated over the unstuffed raw data between, but not including, the last bit in the opening flag and the first bit of the fcs. when the last byte of the message is written into the fifo, the microprocessor must set the end of message status bit eom (bit 2) in register 3dh. this allows the end of the message to be identified to the internal logic, so that it knows where to put the fcs. the computed 16-bit fcs will be appended to the end of the message followed by at least one flag before another message is transmitted. when the transmit pmdl fifo is emptied without setting the eom bit, the fifo will set an underflow indication value of 11 in interrupt request bits irtxfs1 and irtxfs0 (bits 2 and 1) in register 2ch, and an abort character will be transmitted, thereby terminating the message. if the transmit pmdl fifo is emptied after the eom bit is set, then the interrupt request bits irtxfs(1-0) are not set, the fcs is appended to the end of the message as appropriate and then flags are transmitted until another mes- sage is transmitted. the transmit hdlc controller provides interrupt request bits and corresponding interrupt request mask bits related to the transmit pmdl fifo status. information such as underflow and fill status is provided by reading interrupt request bits irtxfs(1-0) (bits 2 and 1 in register 2ch). transmit pmdl fifo service interrupts (irthis bit in bit 0 of register 2ch) may be programmed to occur when the transmit pmdl fifo transitions from more than half full to half empty and/or when the last byte is sent, by setting control bit thie (bit 1) in register 3dh. how an end user might transmit a pmdl message to transmit a pmdl message (79 bytes, excluding flags and fcs-16), first configure the transmitter to gener- ate an interrupt at the end of message by writing a 0 to control bit thie (bit 1) in register 3dh. then write a 1 to control bit eht (bit 0) in register 3dh to enable the transmitter. the transmit pmdl controller will continue to transmit flags until data is written into the transmit pmdl fifo. flags are sent in the selected c-bits in the c-bit parity format ds3 frame as a continuous idle pattern while the transmit pmdl controller is enabled and the transmit pmdl fifo is empty. if the transmit pmdl controller were not enabled then the pmdl c-bits would be derived from either the external c-bit interface or the internal stuffing logic as dictated by the m13mode bit (bit 0 in register 02h). the desired message must be written by the microprocessor into the transmit pmdl fifo by writing each byte in turn into the tx pmdl fifo register in register 37h. bit 0 represents the first bit in the byte to be transmitted. www.datasheet.in - 54 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet the bytes written into the tx pmdl fifo register are transferred automatically into the transmit pmdl fifo by the m13x. after the microprocessor writes the last byte into the transmit pmdl fifo, the microprocessor sets the eom (bit 2) in register 3dh to a 1. the transmit pmdl controller starts processing the message as the pmdl fifo is written, and continues processing until the fifo is empty. if it encounters no eom before the pmdl fifo becomes empty, the message is aborted. since the eom bit was set by the microprocessor, the completion of the message will generate an interrupt, if not masked, as indicated by the interrupt request bit irthis (bit 0) in register 2ch. this latched status indication indicates that the message is complete and another message can be written into the transmit pmdl fifo by the microprocessor. after the fcs-16 is transmitted (and stuffed by the transmit pmdl controller if needed), the hdlc link controller will start to send flags again. it is possible to send proprietary messages longer than 79 bytes (excluding fcs plus opening/closing flags). in this case, the thie bit should be set to a 1. whenever the transmit pmdl fifo transitions from more than half full to half empty, then the irthis bit will signal an interrupt request to tell the external microprocessor that there is room to write more data into the transmit pmdl fifo. this process continues until all of the message has been loaded. just as in the case above, when the last byte of the message is written by the microproces- sor, the eom bit is set by the microprocessor to identify the end of message to the internal logic so that the fcs can be appended to it. how an end user might receive a pmdl message to receive a pmdl message, first configure the receiver to generate an interrupt at the end of message and at the full or overflow level of the receive pmdl fifo by writing a 0 to control bit rhie (bit 5) in register 3dh and writing mask bits mirrhis(2-0) (bits 7 - 5 in register 35h) to 110 and mirrxfs(1-0) (bits 4 and 3 in register 35h) to 11. initialize the receive fifo by reading the rx pmdl fifo register in register 38h repeatedly until the receive pmdl fifo is emptied, which is indicated by rx pmdl fifo depth = 00h in register 3ah. then enable the receiver by writing a 1 to control bit ehr (bit 4) in register 3dh. the receiver will generate an interrupt when the receive pmdl fifo overflows, is full, or a message has been received. a normal, valid received message is indicated by irrhis(2-0) = 010 and irrxfs(1-0) = 00 or 01. the end user must verify that this is the case. the rx pmdl message length register is then read which gives the end user the number of bytes in the message. the end user then reads that number of bytes from the rx pmdl fifo register by initiating multiple read cycles. the rx pmdl message length register should be read no more than 212 s after the irrhis(2-0) bits indicate that a message has been received to ensure that a short message does not cause the rx pmdl message length register to be overwritten before the end user could read it. please note that the rx pmdl message length register is updated when the end of message event indi- cation is latched and an interrupt is generated, and will not be modified until it is read and cleared by the micro- processor or if another completed message is received. the receive pmdl fifo must be read for any type of message termination (good fcs, bad fcs, abort, or invalid frame). if an abort occurs the remainder of the hdlc message is discarded, requiring the end user to clear the receive fifo of the portion of the message indicated by the value in the rx pmdl message length register. care needs to be taken to determine the location of an aborted message in the receive pmdl fifo. this can ascertained by reading both the rx pmdl message length and rx pmdl fifo depth registers. an example is provided to show how to interpret those two registers: an aborted frame is received and an interrupt is signaled via the irrhis(2-0) bits. the rx pmdl fifo depth register is read and found to contain 0ah. the rx pmdl message length register content is read and found to be 07h. this means that there are 3 bytes from a previous frame that need to be read out of the receive pmdl fifo before the current 7-byte aborted frame can be read out. several short messages (such as might occur if several aborted messages are received in succession, or for proprietary messaging) may be left in the receive fifo and read out at a later time. this is accomplished by storing the message length value read from the rx pmdl message length register and the interrupt requests read from irlrhis(2-0) and irlrxfs(1-0) in a queue. the message boundaries and the validity of the messages read from the fifo may be determined from interrupt request and message length values. this www.datasheet.in - 55 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet practice is not recommended since it complicates the process, requires additional resources and takes extra effort to ensure that the receive pmdl fifo does not overflow. if the end user desires to receive a message longer than what could be stored in the receive fifo, the follow- ing procedure can be used: first configure the receiver to generate an interrupt at the end of message or if the receive pmdl fifo becomes full or overflows by writing a 0 to control bit rhie (bit 5) in register 3dh and writ- ing mask bits mirrhis(2-0) (bits 7 - 5 in register 35h) to 110 and mirrxfs1,0 (bits 4 and 3) in register 35h to 11. initialize the receive fifo by reading the rx pmdl fifo register in register 38h repeatedly until the fifo is emptied, which is indicated by rx pmdl fifo depth = 00h in register 3ah. then enable the receiver by writing a 1 to control bit ehr (bit 4) in register 3dh. the receiver will generate an interrupt when the receive pmdl fifo is full or has overflowed or a message has been received. the end of a normal, valid received message is indicated by irrhis(2-0) equal to 010 and irrxfs(1-0) not equal to 10 or 11. when an interrupt occurs, the end user will read the rx pmdl fifo depth register and then the irrxfs(1-0) and the irrhis(2-0) bits. if the irrhis(2-0) and irrxfs(1-0) bits indicate that the end of the message has occurred and receive pmdl fifo full or overflow has not occurred, then the number of bytes indicated by the rx pmdl fifo depth register is read out of the receive pmdl fifo since a complete message has been received. if the irrhis(2-0) bits do not indicate the end of a mes- sage, the irrhis(2-0) bits are checked to see the status of the receive pmdl fifo. if the receive pmdl fifo is half full, then the end user reads out the message segment indicated by the rx pmdl fifo depth register and stores it. this process is repeated until the irrhis(2-0) bits indicate that the end of a message has been received. if an interrupt occurs while reading a message segment from the receive pmdl fifo, the process above should be repeated. in the event that the receive pmdl fifo overflows, the receive pmdl data will be lost. the receive pmdl fifo must be cleared out. an fcs error will not necessarily result due to the loss of the data. this is because the fcs is checked before the pmdl data is written into the receive pmdl fifo. in this case, when the irrxfs(1-0) bits indicate that the receive pmdl fifo has overflowed, the rx pmdl fifo depth register, and perhaps previous values of the rx pmdl message length register (if the receive pmdl fifo was not empty before the current frame was written to the receive pmdl fifo) should be used to calculate how much of the data in the receive pmdl fifo belongs to the corrupted frame. this will allow the end user ? s software to manage the data in the receive pmdl fifo and know which data belongs to a good frame and which belongs to a corrupted frame. counters there are up to eight 8-bit or 16-bit performance counters available in the m13x device depending on the set- ting of the m13x lead. the table below describes counter availability. the address shown in the table is that of the low byte for 16-bit counters. all counters clear when read. all 8-bit counters saturate at a count of ffh. all 16-bit counters saturate at a count of ffffh and have an associated interrupt request bit to indicate when the counter has saturated. two read cycles are needed to read a 16-bit counter. a common register is provided at address 3eh for storing the high (most significant) byte of a 16-bit counter when its low byte is read. that is, when the low (least significant) byte of a 16-bit counter is read, the high byte of that counter is simultaneously written to the common register and can subsequently be read from that register provided that another 16-bit counter read is not performed first. the high byte of a 16-bit counter is not directly accessible via the microprocessor interface; address 3eh must be used to read its contents. www.datasheet.in - 56 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet notes: 1. this counter is not available when p1 and p0 are both set to high. c-bit interfaces transmit and receive ds3 c-bit interfaces are provided for inserting and extracting a set of the ds3 c-bits while operating in c-bit parity format mode. the transmit c-bit interface is comprised of four leads, cckt (clock output), cdt (data input), cdcct (data link indication output), and cfmt (frame output). the following ds3 c-bits are accepted at this interface, c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. a control bit c3clki is provided in bit 7 of register 19h which can enable or disable the clock pulse for the c3 (feac) c-bit. if it is desired to use the internal transmit feac word register (1ch) or the remote loopback register (07h) to transmit feac mes- sages and remote loopback requests, then the c3clki bit should be set to a 1 to disable the c3 c-bit from being supplied by the external ds3 c-bit interface. if it is desired that the c3 c-bit be derived from external logic instead of the transmit feac word register, then the c3clki bit should be set to a 0 to enable the c3 bit to be sourced from the transmit c-bit interface. when the transmit pmdl controller is enabled, c13, c14, and c15 are supplied by the transmit pmdl controller, although cckt will still contain the three clock pulses for those c-bits. when the transmit pmdl controller is disabled, the transmitted c13, c14, and c15 c-bits are taken from the transmit c-bit interface. the receive c-bit interface is comprised of four leads, cckr (clock output), cdr (data output), cdccr (data link indication output), and cfmr (frame output). the following ds3 c-bits are output at this interface: c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. unlike the transmit c-bit interface, all of the indicated c-bits are always available. counter name address (hex) m13x lead counter size (bits) febe performance counter (c-bit parity mode)/ds3 f-bit and m-bit error counter (m13 mode) 04 low 16 c-bit parity performance counter (c-bit parity mode)/ number of rx ds3 frames counter (m13 mode) 05 low 16 p-bit parity performance counter 06 low 16 ds3 f-bit and m-bit error counter 1b low 16 c1 bit equal to zero counter 22 low 16 ds3 m-bit error counter 23 low 16 rx fcs error counter 3b low 16 rx abort counter 3c low 16 febe performance counter (c-bit parity mode)/ds3 f-bit and m-bit error counter (m13 mode) 04 high 8 c-bit parity performance counter (c-bit parity mode)/ number of rx ds3 frames counter (m13 mode) 05 high 8 p-bit parity performance counter 06 high 8 ds3 f-bit and m-bit error counter 1b high 8 c1 bit equal to zero counter (note 1) 22 high 8 ds3 m-bit error counter (note 1) 23 high 8 www.datasheet.in - 57 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet test access port introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. the test access port block, which imple- ments the boundary scan functions, consists of a test access port (tap) controller, instruction and data regis- ters, and a boundary scan register path bordering the input and output leads, as illustrated in 25. the boundary scan test bus interface consists of four input signals (i.e., the test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) input signals) and a test data output (tdo) output signal. a brief description of boundary scan operation is provided below; further information is available in the ieee standard document. the tap controller receives external control information via a test clock (tck) signal, a test mode select (tms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. the instruction and data registers are connected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and data registers and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either register during a scan operation. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals at the device leads to pass to and from the m13x device ? s internal logic, as illustrated in 25. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the bound- ary scan feature is provided in 18. boundary scan support the maximum frequency the m13x device will support for boundary scan is 10 mhz. the m13x device per- forms the following boundary scan test instructions: extest (00) sample/preload (01) bypass (11) idcode (10) it should be noted that the capture - ir state (instruction_capture attribute of bsdl) is ? 01 ? . extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruc- tion is shifted in, the m13x device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external m13x input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the m13x device remains fully operational. while in this test mode, m13x input data, and data destined for device outputs, can be captured and shifted out for inspec- tion. the data is captured in response to control signals sent to the tap controller. www.datasheet.in - 58 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 25. boundary scan schematic bypass test instruction: when the bypass instruction is shifted in, the m13x device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo lead. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. tap controller test data registers instruction register tdi tdo in out boundary scan serial test data core logic of m13x boundary scan register device trs tck tms control leads note: lead locations are shown for illustration only, and do not correspond to the physical device leads. signal input and output leads (solder balls on bottom surface of pbga package) www.datasheet.in - 59 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet idcode test instruction: when the idcode instruction is shifted in, the contents of the idcode register can be read. the idcode register in the tap controller consists of the following four fields: bit 0 is shifted out first. boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. the lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the tap controller. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive the lead high dur- ing test. field bit assignment default value comment m13xrev 31- 28 0000 revision of the m13x (0 h) m13xpartn 27 - 12 0000 1100 1110 1001 m13x part # (03305 = 0ce9 h) m13xmanid 11 - 1 000 0110 1011 m13x manufacturer ? s id (transwitch = 6b h) 1 0 1 required bit www.datasheet.in - 60 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet boundary scan chain there are 177 boundary scan register cells in the boundary scan chain. scan cell number 0 is defined as the cell nearest the tdo lead and is therefore the first to be shifted out. the last scan cell to be shifted out is num- ber 177. bidirectional signals require two scan cells. additional scan cells are used for direction control as needed. the following table shows the listed order of the scan cells and their function. bsdl files are made available via the product software page of the transwitch internet world wide web site at www.transwitch.com as they are released. scan cell no. i/o lead no. pqfp lead no. pbga symbol comments i 149 c16 tdi [scan input] 176 i 161 a15 p1 input 175 i 162 b14 p0 input 174 -- -- -- -- tri-state control for cell 173. 1 = tri-state. 173 o 163 a14 rdy/dtack output3 172 -- -- -- -- internal. always set to a 0. 171 -- -- -- -- internal. always set to a 1. 170 i 165 c13 dt12 input 169 i 167 d13 ct5 input 168 i 168 b12 dt5 input 167 i 169 a12 ct6 input 166 i 170 c12 dt6 input 165 i 171 d12 ct7 input 164 i 172 b11 dt7 input 163 i 173 a11 ct8 input 162 i 174 c11 dt8 input 161 i 175 b10 ct1 input 160 i 176 a10 dt1 input 159 i 177 c10 ct2 input 158 i 178 d10 dt2 input 157 i 179 a9 ct3 input 156 i 180 b9 dt3 input 155 i 181 c9 ct4 input 154 i 182 d9 dt4 input 153 -- -- -- -- tri-state control for crn and drn outputs. 1 = tri-state. 152 o 184 c8 cr19 output3 151 o 185 a8 dr20 output3 150 o 186 b8 cr20 output3 note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 61 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 149 o 187 d7 dr21 output3 148 o 188 c7 cr21 output3 147 o 189 a7 dr22 output3 146 o 190 b7 cr22 output3 145 o 192 d6 dr23 output3 144 o 193 c6 cr23 output3 143 o 194 a6 dr24 output3 142 o 195 b6 cr24 output3 141 o 196 d5 dr25 output3 140 o 197 c5 cr25 output3 139 -- -- -- -- tri-state control for cells 138 and 81. 1 = tri-state. 138 o 198 a5 cdcct output3 137 o 199 b5 dr26 output3 136 o 201 a4 cr26 output3 135 o 202 b4 dr27 output3 134 o 203 a3 cr27 output3 133 i 204 b3 dlen input. cell 139 is used to control cdccr and cdcct. 132 i 207 b2 hreset input 131 i 3 c3 m13x input 130 -- -- -- -- tri-state control for cell 129. 1 = tri-state. 129 o 4 b1 int/irq output3 128 o 6 c2 dr28 output3 127 o 7 d2 cr28 output3 126 o 8 d3 dr19 output3 125 o 9 d1 cr18 output3 124 o 10 d4 dr18 output3 123 o 11 e2 cr17 output3 122 o 12 e1 dr17 output3 121 o 13 e3 cr16 output3 120 o 14 e4 dr16 output3 119 o 15 f2 cr15 output3 118 o 16 f1 dr15 output3 117 o 17 f3 cr14 output3 scan cell no. i/o lead no. pqfp lead no. pbga symbol comments note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 62 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 116 o 19 g2 dr14 output3 115 o 20 g1 cr13 output3 114 o 21 g3 dr13 output3 113 o 22 g4 cr12 output3 112 o 23 h2 dr12 output3 111 o 24 h1 cr11 output3 110 o 25 h3 dr11 output3 109 o 26 h4 cr10 output3 108 o 27 j4 dr10 output3 107 o 28 j3 cr9 output3 106 o 29 j1 dr9 output3 105 o 30 j2 cr8 output3 104 o 31 k4 dr8 output3 103 -- -- -- -- internal. always set to 1. 102 o 33 l4 cr7 output3 101 o 34 l3 dr7 output3 100 o 35 l1 cr6 output3 99 o 36 l2 dr6 output3 98 o 37 m4 cr5 output3 97 o 38 m3 dr5 output3 96 o 39 m1 cr4 output3 95 o 40 m2 dr4 output3 94 o 41 n3 cr3 output3 93 o 42 n1 dr3 output3 92 o 43 n2 cr2 output3 91 o 44 p1 dr2 output3 90 i 45 p2 a0 input 89 i 46 r1 a1 input 88 i 47 t1 a2 input 87 i 48 r2 a3 input 86 -- -- -- -- internal. always set to 1. 85 i 57 r3 a4 input 84 i 58 t3 a5 input 83 i 59 r4 a6 input 82 i 60 p4 a7 input scan cell no. i/o lead no. pqfp lead no. pbga symbol comments note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 63 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 81 o 61 t4 cdccr output3 80 o 62 n4 cr1 output3 79 o 63 r5 dr1 output3 78 o 64 t5 cfmr output2 77 o 65 p5 cckr output2 76 o 66 n5 cdr output2 75 i 68 t6 ds3cr input 74 i 69 p6 ds3dr input 73 i 71 p7 rd ,rd/wr input 72 i 72 n7 wr input 71 i 73 r8 ale input 70 i 74 t8 sel input 69 -- -- -- -- tri-state control for cells 67, 65, 63, 61, 59, 57, 55, and 53. 1 = tri-state. 68 i/o 76 n8 a/d7 d7 input 67 i/o 76 n8 a/d7 d7 output3 66 i/o 77 n9 a/d6 d6 input 65 i/o 77 n9 a/d6 d6 output3 64 i/o 78 p9 a/d5 d5 input 63 i/o 78 p9 a/d5 d5 output3 62 i/o 79 t9 a/d4 d4 input 61 i/o 79 t9 a/d4 d4 output3 60 i/o 80 r9 a/d3 d3 input 59 i/o 80 r9 a/d3 d3 output3 58 i/o 81 n10 a/d2 d2 input 57 i/o 81 n10 a/d2 d2 output3 56 i/o 82 p10 a/d1 d1 input 55 i/o 82 p10 a/d1 d1 output3 54 i/o 83 t10 a/d0 d0 input 53 i/o 83 t10 a/d0 d0 output3 52 -- -- -- -- internal. always set to 1. 51 i 85 n11 s7 input 50 i 86 p11 s6 input 49 i 87 t11 s5 input 48 i 89 n12 cdt input scan cell no. i/o lead no. pqfp lead no. pbga symbol comments note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 64 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 47 i 90 p12 xck input 46 o 91 t12 cfmt output2 45 o 92 r12 cckt output2 44 o 93 p13 ds3dt output2 43 i 95 t13 ct25 input 42 i 96 t14 dt25 input 41 i 97 r14 ct26 input 40 i 98 t15 dt26 input 39 i 99 t16 ct27 input 38 i 100 r15 dt27 input 37 -- -- -- -- internal. always set to 1. 36 i 108 p14 ct28 input 35 i 109 r16 dt28 input 34 i 111 p16 ct21 input 33 i 112 n15 dt21 input 32 i 113 n14 ct22 input 31 i 114 n16 dt22 input 30 i 115 n13 ct23 input 29 i 116 m15 dt23 input 28 i 117 m16 ct24 input 27 i 118 m14 dt24 input 26 i 119 m13 ct17 input 25 i 120 l15 dt17 input 24 i 121 l16 ct18 input 23 i 122 l14 dt18 input 22 i 123 l13 ct19 input 21 o 125 k16 ds3ct output2 20 i 127 k13 dt19 input 19 i 128 j15 ct20 input 18 i 129 j16 dt20 input 17 i 130 j14 ct13 input 16 i 131 j13 dt13 input 15 i 132 h13 ct14 input 14 i 133 h14 dt14 input 13 i 134 h16 ct15 input scan cell no. i/o lead no. pqfp lead no. pbga symbol comments note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 65 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 12 i 135 h15 dt15 input 11 i 136 g13 ct16 input 10 i 137 g14 dt16 input 9 i 139 f14 ct9 input 8 i 140 f16 dt9 input 7 i 141 f15 ct10 input 6 i 142 e13 dt10 input 5 i 143 e14 ct11 input 4 i 144 e16 txfrm input 3 i 145 e15 dt11 input 2 i 147 d15 ct12 input 1 -- -- -- -- internal. always set to 1. 0 -- -- -- -- internal. always set to 1. 2-state 150 c15 tdo [scan output] scan cell no. i/o lead no. pqfp lead no. pbga symbol comments note: the comments column indicates the functional operation of the corresponding lead. www.datasheet.in - 66 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet software initialization sequence the following table lists the sequence that should be followed for initializing the m13x by writing codes to regis- ter 1fh: system considerations careful attention must be paid to power supply decoupling, device layout, and printed circuit board traces. the m13x has separate +5 volt supply (v dd ) leads which provide internal circuit isolation. all v dd leads must be tied together to a single +5 volt power supply in order to avoid excessive substrate currents. transwitch recom- mends that good quality, high frequency, low lead inductance 0.1 microfarad ceramic capacitors be used for decoupling and that they be connected in close proximity to the supply input leads on the device. a decoupling capacitor should be used at each power supply input lead. if low frequency noise is present on the +5 volt sup- ply lead, transwitch recommends that a 10 microfarad 6.3 volt tantalum capacitor be connected between +5 volts and ground. a multilayer board that has separate planes for ground and power should be used. because of the high data rate at which the m13x operates, it is important that connections between devices be as short as possible. this is especially true for the ds3 receive and transmit interface connections between the m13x and a line interface device, such as the transwitch art, arte, dart or ds3lim-sn. in addition, the clock and data traces should be the same length. throughput delays the data transmission paths of the m13x device are subject to throughput delays from input to output, as iden- tified in the following table: register address code (hex) comments 1f (r/w) f0 resets internal counters and fifos. 1f (r/w) 00 presets internal counters and fifos. direction from to delay (min.) delay (typ.) delay (max.) notes receive (djb enabled) ds3dr drn 9920 ns 10520 ns n = 1 - 28 receive (djb disabled) ds3dr drn 200 ns 800 ns n = 1 - 28 transmit dtn ds3dt 400 ns 4100 ns 7800 ns n = 1 - 28 www.datasheet.in - 67 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet memory map the m13x memory map consists of control bits, alarms (non-latched and latched), and counters that can be accessed via the microprocessor interface. the unused bit positions in a register (shown shaded in the table below) must be masked by software to avoid reading incorrect data. in r/w registers, the shaded positions should be written with a 0. at power-up the memory map will remain random until a hardware reset is initiated via the hreset lead or a soft reset is applied via register 1fh. this register location is used to reset and ini- tialize the m13x. after power becomes stable, a f0 hex followed by a 00 hex must be written into 1fh. address (hex) mode (see note 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 r r3los r3oof r3ais r3idl r3ckf t3ckf xr2 xr1 01 r/w test bit test bit t3ais t3idl febe pbite cbite xt 02 r/w idlb idla test bit 3lbk lptime invck 1inv m13mode 03 r cbit1 ds2oof7 ds2oof6 ds2oof5 ds2oof4 ds2oof3 ds2oof2 ds2oof1 04 r fbn: febe performance counter (c-bit parity mode) / ds3 f-bit and m-bit error counter (m13 mode) 05 r cpn: c-bit parity performance counter (c-bit parity mode) / number of rx ds3 frames counter (m13 mode) 06 r ppn: p-bit parity performance counter 07 r/w exec con/dis lbsel d22 d21 d20 d11 d10 08 r lball lb25 lb21 lb17 lb13 lb9 lb5 lb1 09 r lbds3 lb26 lb22 lb18 lb14 lb10 lb6 lb2 0a r lb27 lb23 lb19 lb15 lb11 lb7 lb3 0b r lb28 lb24 lb20 lb16 lb12 lb8 lb4 0c r los25 los21 los17 los13 los9 los5 los1 0d r los26 los22 los18 los14 los10 los6 los2 0e r los27 los23 los19 los15 los11 los7 los3 0f r los28 los24 los20 los16 los12 los8 los4 10 r/w m13xid0 idl25 idl21 idl17 idl13 idl9 idl5 idl1 11 r/w idl26 idl22 idl18 idl14 idl10 idl6 idl2 12 r/w idl27 idl23 idl19 idl15 idl11 idl7 idl3 13 r/w idl28 idl24 idl20 idl16 idl12 idl8 idl4 14 r r2x7 r2x6 r2x5 r2x4 r2x3 r2x2 r2x1 15 r/w t2x7 t2x6 t2x5 t2x4 t2x3 t2x2 t2x1 16 r(l) r3los r3oof r3ais r3idl r3ckf t3ckf xr2 xr1 17 r(l) cerror ds2oof7 ds2oof6 ds2oof5 ds2oof4 ds2oof3 ds2oof2 ds2oof1 18 test bits 19 r/w c3clki test bits 1a r rhis(2-0) rxfs(1-0) txfs(1-0) 1b r fmen: ds3 f-bit and m-bit error counter 1c r/w exec cont/10 tfeac6 tfeac5 tfeac4 tfeac3 tfeac2 tfeac1 1d r fidl new rfeac6 rfeac5 rfeac4 rfeac3 rfeac2 rfeac1 1e r/w exec con/dis llb22 llb21 llb20 llb11 llb10 1f r/w reset and test register mux (see note 2) 20 r/w 1trist 1lossel 1tais1 1tais0 1lbv3 1lbv2 1lbv1 1lbv0 21 r/w r3ais2 r3ais1 r3ais0 t3ais1 t3ais0 22 r c1bzn: c1 bit equal to zero counter 23 r men: ds3 m-bits in error counter www.datasheet.in - 68 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet notes: 1. read/write (r/w); read -only (r); read-only - latched register r(l). 2. f0h followed by 00h resets the entire device. 24 r(l) aisxeq1 aisceq0 test bits sef 25 r(l) irlball irlb25 irlb21 irlb17 irlb13 irlb9 irlb5 irlb1 26 r(l) irlbds3 irlb26 irlb22 irlb18 irlb14 irlb10 irlb6 irlb2 27 r(l) irnew irlb27 irlb23 irlb19 irlb15 irlb11 irlb7 irlb3 28 r(l) irsef irlb28 irlb24 irlb20 irlb16 irlb12 irlb8 irlb4 29 r(l) irr3los irr3oof irr3ais irr3idl irr3ckf irt3ckf irxr2 irxr1 2a r(l) ircerror irds2oof7 irds2oof6 irds2oof5 irds2oof4 irds2oof3 irds2oof2 irds2oof1 2b r(l) irfcss irabts irfbs ircps irpps irfmes irc1bzs irmes 2c r(l) irrhis(2-0) irrxfs(1-0) irtxfs(1-0) irthis 2d r(l) 2e r/w mirlball mirlb25 mirlb21 mirlb17 mirlb13 mirlb9 mirlb5 mirlb1 2f r/w mirlbds3 mirlb26 mirlb22 mirlb18 mirlb14 mirlb10 mirlb6 mirlb2 30 r/w mirnew mirlb27 mirlb23 mirlb19 mirlb15 mirlb11 mirlb7 mirlb3 31 r/w mirsef mirlb28 mirlb24 mirlb20 mirlb16 mirlb12 mirlb8 mirlb4 32 r/w mirr3los mirr3oof mirr3ais mirr3idl mirr3ckf mirt3ckf mirxr2 mirxr1 33 r/w mircerror mirds2oof7 mirds2oof6 mirds2oof5 mirds2oof4 mirds2oof3 mirds2oof2 mirds2oof1 34 r/w mirfcss mirabts mirfbs mircps mirpps mirfmes mirc1bzs mirmes 35 r/w mirrhis(2-0) mirrxfs(1-0) mirtxfs(1-0) mirthis 36 r/w 37 w tx pmdl fifo (interface register for writing bytes to transmit pmdl fifo) 38 r rx pmdl fifo (interface register for reading bytes from receive pmdl fifo) 39 r rx pmdl message length 3a r rx pmdl fifo depth 3b r rx fcs error counter 3c r rx abort counter 3d r/w djb ipolal rhie ehr -- eom thie eht 3e r cr: common register for high order counter byte 3f r/w rise fall address (hex) mode (see note 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.in - 69 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet memory map descriptions address bit symbol description 00 7 r3los receive ds3 loss of signal: a receive ds3 los alarm occurs, and this bit is set to 1, when the incoming ds3 data (ds3dr) is stuck low for more than 1020 ds3cr clock cycles. recovery to 0 occurs when two or more ones are detected in the incoming data bit stream. this bit is intended for board diagnostics and is not meant to indicate a los on the ds3 line sig- nal. this bit position is unlatched. 6r3oof receive ds3 out of frame: a receive oof alarm occurs, and this bit is set to 1, when three out of 16 f-bits are in error utilizing a sliding window of 16 ds3 f-bits, or one or more m-bits are in error in two consecutive frames. recovery to 0 occurs when the f framing pattern of 1001 is detected, and the m framing pattern of 010 is detected for two consecutive frames. recov- ery takes approximately 0.95 milliseconds, worst case. this bit position is unlatched. an oof also inhibits the performance counters (04h, 05h, 06h, 1bh, 22h, 23h, 3bh, and 3ch). 5r3ais receive ais alarm indication signal: the m13x detects ds3 ais by five methods. the method of detection that drives the r3ais alarm, and sets this bit to 1, is selected by the states written to the three r3aisn bits in register 21h. this bit position is unlatched. when the m13x is configured to detect one of the framed ais signals (selected via bits 4-2 of register 21h), the r3oof bit (bit 6 of this register) should be examined to ensure that the m13x is detecting ds3 frame. 4r3idl receive ds3 idle pattern signal: a ds3 idle pattern signal has a valid m- frame alignment channel, m-subframe alignment channel, and p-bit chan- nel. the information bits are a 1100 sequence that starts with 11 after each m-frame alignment, m-subframe alignment, x-bit, p-bit, and c-bit channels. the c-bits (c7, c8, and c9) in m-subframe 3 are set to 0. a valid received ds3 idle signal is detected, and this bit is set to 1, when the m13x detects zeros for c7, c8, and c9 in subframe 3 and the 1100 sequence. the m13x searches for the 1100 pattern sequence on a per ds3 frame basis. the m13x can tolerate up to and including 5 errored 4-bit groups of the 1100 pattern per ds3 frame and still recognize the 1100 pattern as valid. if the m13x detects 6 or more errored 4-bit groups of the 1100 pattern per ds3 frame the m13x will exit the r3idl state and this bit will reset to 0. this bit position is unlatched. a ds3 idle signal as defined in ansi t1.107-1995 is being received by the m13x device if this bit and bits 1 and 0 of this register are all set to 1. 3r3ckf receive ds3 clock failure: a receive ds3 clock failure alarm occurs, and this bit is set to 1, when the receive clock (ds3cr) is stuck high or low for 6-7 xck clock cycles. recovery to 0 occurs when the ds3cr clock returns for one cycle. the demultiplexer does not function when the receive clock is lost. the ds3cr lead is still monitored for this alarm during ds3 local loop- back (control bit 3lbk = 1), so that it may be necessary to set control bits 1tais1 and 1tais0 to 11 to prevent ais insertions into the receive ds1 data stream. this bit position is unlatched. www.datasheet.in - 70 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 00 (cont.) 2t3ckf transmit ds3 clock failure: a transmit ds3 clock failure alarm occurs, and this bit is set to 1, when the transmit input clock (xck) is stuck high or low for 6-7 ds3cr clock cycles. a failure causes the receive clock to become the transmit clock. this permits the m13x microprocessor interface, multiplexer, and djb logic to function. recovery to 0 occurs when the xck clock returns for one cycle. 1xr2 receive ds3 x-bit number 2: this bit position indicates the receive state of x2. this bit position is updated each frame. 0xr1 receive ds3 x-bit number 1: this bit position indicates the receive state of x1. this bit position is updated each frame. 01 7 test bit reserved for transwitch testing purposes: a 0 must be written into this bit position. 6test bit reserved for transwitch testing purposes: a 0 must be written into this bit position. 5t3ais transmit ds3 alarm indication signal: a 1 causes the m13x to transmit a ds3 ais. the type of ais sent is determined by the states written into bit 1 (t3ais1) and bit 0 (t3ais0) in register 21h. 4t3idl transmit ds3 idle signal: to transmit a ds3 idle signal, (i) a 1 must be written in this bit 4 (t3idl) register location, and (ii) a 1 must also be written (if not already written) into bit 0 (xt) of this register 01h, and (iii) bit 0 (t3ais0) and bit 1 (t3ais1) of register 21h must also be set to 0. 3febe transmit far end block error: a 1 causes the m13x to transmit a single febe error indication (c10, c11, and c12 equal to 0) in the next ds3 frame. this bit is not self-clearing; to send an additional febe indication, the microprocessor must first write this bit with a 0 and then with a 1. 2 pbite transmit p-bit parity error: a 1 causes the m13x to transmit a single p- bit parity error in the next ds3 frame. the p-bit error is transmitted by inverting the value of the two calculated bits. this bit is not self-clearing; to send an additional error, the microprocessor must first write this bit with a 0 and then with a 1. 1cbite transmit c-bit parity error: a 1 causes the m13x to transmit a single c- bit parity error in the next available ds3 frame when the m13x is operating in the c-bit parity mode. the c-bit error is transmitted by inverting the calcu- lated c-bit parity bits in subframe 3 (c7, c8, and c9). this bit is not self- clearing; to send an additional error, the microprocessor must first write this bit with a 0 and then with a 1. 0xt transmit x-bits: the x-bits may be used to transmit a yellow alarm or may be used as a low speed signaling channel. a 1 or 0 causes the m13x to transmit a 1 or 0 for both x1 and x2. note: this bit must be set to 1 when transmitting ds3 idle signal (see t3idl, bit 4 in this register 01h). address bit symbol description www.datasheet.in - 71 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 02 7 6 idlb idla ds1 idle code selection: three ds1 idle codes are provided, as shown in the table below. the idle code selected via these control bits is common to all ds1 channels selected for idle code transmission. one or more transmit- ted ds1 channels is selected by writing a 1 in the corresponding idln bit(s) in register locations 10h, 11h, 12h, and 13h, provided register location 1eh has not been set so as to select that ds1 channel for loopback. 5test bit reserved for transwitch testing purposes: a 0 must be written into this bit position. 43lbk ds3 local loopback: a 1 disables the ds3 receive input and causes the ds3 transmit output to be looped back as receive data. transmit data is provided at the output (ds3dt). please note that the ds3cr lead is still monitored for a r3ckf alarm 3lptime receive loop timing: a 1 disables the external transmit clock input (xck), and causes the ds3 receive clock to become the ds3 transmit clock. if the ds3 receive clock fails in this mode, the m13x switches over to the transmit clock (xck). the demultiplexer becomes inoperative, but the multiplexer and microprocessor interface continue to function. 2invck invert ds1 transmit clocks: a 1 causes all transmit ds1 data inputs (dtn) to be sampled on the falling edges of their respective ds1 clock inputs (ctn). this is provided for back-to-back m13x operation. 11inv invert ds1 transmit data: a 1 causes the transmit data inputs for all ds1 channels (dtn) to be inverted within the m13x. 0m13mode m13 operating mode: a 1 enables the m13x to operate in the m13 format mode. using ansi t1.107-1995 terminology, the m13x performs m12 mode and m23 mode muxing and demuxing where the ds2 and ds3 c- bits are used for stuffing/destuffing. a 0 enables the m13x to operate in the c-bit parity mode as specified in the ansi t1.107-1995. 03 7 cbit1 c-bit number 1 state: this bit is updated each frame with the state of the received c1 bit. the c1 bit is used to identify the ds3 application according to the table shown below: in addition, any c-bit that is received as 0 will increment the c-bit equal to zero counter in register 22h. address bit symbol description idlb idla ds1 idle code selected 0 0 quasi-random signal (2 20 - 1 qrs) including zero suppression. 1 0 framed extended super frame (esf) signal format which consists of an s-bit pattern of 001011 in every fourth signaling bit position, crc-6 pattern, and ones in the 64 kbit/s channels 1 through 24. x 1 unframed all ones signal (ais). c1 value application random m13 format all 1s c-bit parity format www.datasheet.in - 72 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 03 (cont.) 6-0 ds2oofn (n=7-1) ds2 out of frame alarm indication: a 1 in bits 6-0 corresponds to an out of frame alarm for the corresponding ds2 channel (7-1). a ds2 oof occurs when two out of four consecutive framing bits are in error. a ds2 oof for a ds2 channel causes ais to be inserted into its four ds1 chan- nels when 1tais1, 1tais0 = 0, 0 or 0, 1 in register 20h, bits 5 and 4. recovery to 0 is based on searching for the 0101 framing pattern. framing is accomplished by starting at an arbitrary point with the first received bit (0 or 1) and looking 147 (3x49) bit positions later for the bit of opposite sense. this search is performed for 12 bit positions simultaneously. once the fram- ing pattern is found, one more frame is used to acquire alignment. recov- ery takes approximately 6.8 milliseconds, worst case average. 04 7-0 fbn (n=7-0) febe performance counter/ds3 f-bit and m-bit error counter: this performance counter counts the number of febes received since the last read cycle in the c-bit parity mode. a febe indication occurs when c10, c11, or c12 is received equal to 0 in a ds3 frame. the counter is protected during the period of a microprocessor read cycle and when the m13x is attempting to write to the counter. when this occurs, the incoming error count indication is held until the counter is read and cleared. afterwards, the counter increments. only the indication of one error count is held during the microprocessor read and the m13x write cycle. the counter is also inhibited during ds3 loss of signal or out of frame times. this counter is cleared when it is read by the microprocessor. in the m13 format mode, this saturating counter counts the number of ds3 f-bits and m-bits that have been received in error. this counter is inhibited when a ds3 oof occurs and clears when read. when lead m13x is low, this counter is 16 bits wide and this address contains the low byte of the counter. the high byte of this counter is written to the cr register (3eh) when this register is read. when m13x is high, this counter is 8 bits wide. 05 7-0 cpn (n=7-0) c-bit parity performance/number of frames counter: in the c-bit parity mode, this counter counts the number of c-bit parity errors received since the last read cycle. in the m13 format mode, it counts the number of ds3 frames since the last read cycle. the counter is protected during the period of a microprocessor read cycle and when the m13x is attempting to write to the counter. when this occurs, the incoming error count indication is held until the counter is read and cleared. afterwards, the counter increments. only the indication of one error count is held during the microprocessor read and the m13x write cycle. the counter is inhibited during ds3 loss of signal or out of frame times, and is cleared when it is read by the micropro- cessor. when lead m13x is low, this counter is 16 bits wide and this address contains the low byte of the counter. the high byte of this counter is written to the cr register (3eh) when this register is read. when m13x is high, this counter is 8 bits wide. 06 7-0 ppn (n=7-0) p-bit parity performance counter: this counter counts the number of p-bit parity errors received since the last read cycle. this performance count is valid in either operating mode. the counter is protected during the period of a microprocessor read cycle and when the m13x is attempting to write to the counter. when this occurs, the incoming error count indication is held until the counter is read and cleared. afterward, the counter incre- ments. only the indication of one error count is held during the micropro- cessor read and the m13x write cycle. the counter is also inhibited during ds3 loss of signal or out of frame times. this counter is cleared when it is read by the microprocessor. when lead m13x is low, this counter is 16 bits wide and this address contains the low byte of the counter. the high byte of this counter is written to the cr register (3eh) when this register is read. when m13x is high, this counter is 8 bits wide. address bit symbol description www.datasheet.in - 73 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 07 7 6 5 4 3 2 1 0 exec con/dis lbsel d22 d21 d20 d11 d10 remote loopback: the bits in this location are used to send a ds1 remote loopback request in the m13 format mode, or a ds3/ds1 remote loopback request in the c-bit parity mode (see note 1). bit 7 (exec) exe- cutes the command. bit 6 (con/dis, see note 2) selects the command to connect or disconnect the loopback selected. when in c-bit parity mode bit 5 (lbsel) selects either ds2 c or stuff bit inversions, defined by the four 1lbvn bits in register 20h or a double feac message (in c-bit parity mode only) when sending a loopback request. the ds2 c or stuff bit inversion mechanism in the m13 (or c-bit parity) format mode is selected by the states written to the four 1lbvn bits in register 20h. bits 4 (d22), 3 (d21), and 2 (d20) select the ds2 channels (1-7). bits 1 (d11) and 0 (d10) select one of four ds1 channels. in the c-bit parity mode, the feac channel (c3) can be used for sending ds1 and ds3 remote loopback requests. the channel to be looped is written into bits 4-0. the m13x translates this code into the feac codeword. to send a loopback request using the feac channel, the m13x sends 10 repetitions of the feac line activator code sequence (0 000111 0 11111111) followed immediately by 10 repetitions of the loopback codeword (0 xxxxxx 0 11111111). at the end of this sequence (20 codewords or 320 ds3 frames), completion is indicated by bit 7 (exec) resetting to 0. to deactivate a loopback using the feac channel, the m13x sends 10 repetitions of the deactivate code followed immediately by 10 rep- etitions of the channel selected. the codes for sending and deactivating a remote loopback request are shown below: notes: for con/dis, connect = 1, disconnect = 0 for x, 1 = feac (c-bit parity mode only), 0 = ds2 c or stuff bit inversion notes: 1. if this register is used to send a remote loopback request using the double word feac message then the c3clki bit in register 19 hex must be set to a 1. 2. con/dis is not used when lbsel = 0. instead, bit 7 (exec) is used when lbsel = 0 to send (exec = 1) or stop sending (exec = 0) a remote loopback request via the ds2 c or stuff bit inversions defined by register 20h bits 3-0. if a loopback request for a different channel is sent via register 07h (that uses ds2 c or stuff bit inversion), the current transmitted loopback request is taken down. i.e. only single loopback requests can be sent one at a time unless the ? all ? loopback request command is used. when the ? all ? loopback request command is used, loopback requests for all channels are simultaneously transmitted. address bit symbol description bits 7 6 5 4 3 2 1 0 channel exec con/dis lbsel d22 d21 d20 d11 d10 all 1 1 or 0 x 000 0 0 channel 1 1 1 or 0 x 0 0 1 0 0 channel 2 1 1 or 0 x 0 0 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - channel 28 1 1 or 0 x 1 1 1 1 1 ds3 1 1 or 0 1 000 1 0 www.datasheet.in - 74 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 08 7 6 5 4 3 2 1 0 lball lb25 lb21 lb17 lb13 lb9 lb5 lb1 receive loopback requests: bit 7, lball (all ds1 channels), bits 6-0 (lbn), and registers 09h through 0bh indicate the loopback request detected. for the m13 format mode, a loopback request is received when any of the conditions (ds2 c-bit or stuff) are detected five or more times in succession. the remote loopback selection is determined by the states written to the 1lbvn bits in register location 20h. a remote loopback request is cancelled when the normal state of the bit is received five or more times in succession. in the c-bit parity mode, a remote loopback request is received by detecting the feac connect word five times in suc- cession, followed by five consecutive receptions of the ds1 channel num- ber word. a remote loopback request is cleared upon the reception of five consecutive disconnect feac messages followed by the reception of the ds1 channel number word. the m13x will also respond to the conditions (ds2 c-bit or stuff) set up by the 1lbvn bits in register location 20h while in c-bit parity mode. note: it is possible to have multiple loopbacks set. once a loopback request is received or taken down in registers 08h-0bh, the microprocessor must write the appropriate code to register 1eh to cor- respondingly set up or take down the loopback in the appropriate ds1 channel. when detecting loopback requests via the mechanism indicated by the 1lbvn bits in register 20h, the m13x must have ds2 and ds3 frame syn- chronization. when detecting loopback requests via the feac channel, the m13x must have ds3 frame synchronization and not be receiving ds3 ais or ds3 idle signals. lball is valid only in c-bit parity mode. 09 7 6 5 4 3 2 1 0 lbds3 lb26 lb22 lb18 lb14 lb10 lb6 lb2 receive loopback requests: bits 7 (lbds3), 6-0 (lbn), and registers 08h, 0ah and 0bh indicate loopback requests sent by the distant end for either a ds3 loopback or for the ds1 channels indicated. for complete explanation, see 08h. lbds3 is valid only in c-bit parity mode. 0a 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 lb27 lb23 lb19 lb15 lb11 lb7 lb3 receive loopback requests: bits 6-0 (lbn) and registers 08h, 09h and 0bh indicate loopback requests sent by the distant end for the ds1 chan- nels indicated. for complete explanation, see 08h. 0b 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 lb28 lb24 lb20 lb16 lb12 lb8 lb4 receive loopback requests: bits 6-0 (lbn) and registers 08h through 0ah indicate loopback requests sent by the distant end for the ds1 chan- nels indicated. for complete explanation, see 08h. address bit symbol description www.datasheet.in - 75 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 0c 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 los25 los21 los17 los13 los9 los5 los1 loss of signal, ds1 channel n: each ds1 channel is monitored for loss of signal, which sets the associated bit losn to 1. the selection of monitor- ing transmit ds1 channels or receive ds1 channels is determined by the state written to control bit 1lossel, bit 6 in register 20h. a 1 selects the transmit ds1 channels. a ds1 channel loss of signal is defined as between eight and sixteen ds2 frames of consecutive 0s. recovery occurs after the first 1 is detected. 0d 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 los26 los22 los18 los14 los10 los6 los2 loss of signal, ds1 channel n: each ds1 channel is monitored for loss of signal, which sets the associated bit losn to 1. the selection of monitor- ing transmit ds1 channels or receive ds1 channels is determined by the state written to control bit 1lossel, bit 6 in register 20h. a 1 selects the transmit ds1 channels. a ds1 channel loss of signal is defined as between eight and sixteen ds2 frames of consecutive 0s. recovery occurs after the first 1 is detected. 0e 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 los27 los23 los19 los15 los11 los7 los3 loss of signal, ds1 channel n: each ds1 channel is monitored for loss of signal, which sets the associated bit losn to 1. the selection of monitor- ing transmit ds1 channels or receive ds1 channels is determined by the state written to control bit 1lossel, bit 6 in register 20h. a 1 selects the transmit ds1 channels. a ds1 channel loss of signal is defined as between eight and sixteen ds2 frames of consecutive 0s. recovery occurs after the first 1 is detected. 0f 7 reserved reserved: this bit should always be ignored. 6 5 4 3 2 1 0 los28 los24 los20 los16 los12 los8 los4 loss of signal, ds1 channel n: each ds1 channel is monitored for loss of signal, which sets the associated bit losn to 1. the selection of monitor- ing transmit ds1 channels or receive ds1 channels is determined by the state written to control bit 1lossel, bit 6 in register 20h. a 1 selects the transmit ds1 channels. a ds1 channel loss of signal is defined as between eight and sixteen ds2 frames of consecutive 0s. recovery occurs after the first 1 is detected. 10 7 m13xid0 device id 0: this bit is used to identify whether an m13x or an m13e device is installed in an application. if this bit is always 0 then the device is an m13x device. if this bit is a read/write bit then it is an m13e device. the m13e device is the predecessor of the m13x device. 6 5 4 3 2 1 0 idl25 idl21 idl17 idl13 idl9 idl5 idl1 internal ds1 idle channel/loopback: the idln bits in this register are used for generating and transmitting a ds1 idle pattern or for setting up a local ds1 loopback for channel n. when register 1eh is written with a code to disconnect the loopback on a channel in this register, and the corre- sponding idln bit is written with a 1, the m13x generates and transmits a ds1 idle pattern in that channel which is determined by the idle code selec- tion bits (idlb and idla in location 02h). when a code to connect a loop- back on a channel in this register is written to register 1eh, and a 1 is written into the corresponding idln bit, the ds1 channel is looped back instead. the loopback is from the receive to the transmit direction. when the idln bit is written with a 0, the ds1 transmit source is from the chan- nel ? s dtn/ctn leads. address bit symbol description www.datasheet.in - 76 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 11 7 reserved reserved: this bit should always be written with a 0. 6 5 4 3 2 1 0 idl26 idl22 idl18 idl14 idl10 idl6 idl2 internal ds1 idle channel/loopback: the idln bits in this register are used for generating and transmitting a ds1 idle pattern or for setting up a local ds1 loopback for channel n. when register 1eh is written with a code to disconnect the loopback on a channel in this register, and the corre- sponding idln bit is written with a 1, the m13x generates and transmits a ds1 idle pattern in that channel which is determined by the idle code selec- tion bits (idlb and idla in location 02h). when a code to connect a loop- back on a channel in this register is written to register 1eh, and a 1 is written into the corresponding idln bit, the ds1 channel is looped back instead. the loopback is from the receive to the transmit direction. when the idln bit is written with a 0, the ds1 transmit source is from the chan- nel ? s dtn/ctn leads. 12 7 reserved reserved: this bit should always be written with a 0. 6 5 4 3 2 1 0 idl27 idl23 idl19 idl15 idl11 idl7 idl3 internal ds1 idle channel/loopback: the idln bits in this register are used for generating and transmitting a ds1 idle pattern or for setting up a local ds1 loopback for channel n. when register 1eh is written with a code to disconnect the loopback on a channel in this register, and the corre- sponding idln bit is written with a 1, the m13x generates and transmits a ds1 idle pattern in that channel which is determined by the idle code selec- tion bits (idlb and idla in location 02h). when a code to connect a loop- back on a channel in this register is written to register 1eh, and a 1 is written into the corresponding idln bit, the ds1 channel is looped back instead. the loopback is from the receive to the transmit direction. when the idln bit is written with a 0, the ds1 transmit source is from the chan- nel ? s dtn/ctn leads. 13 7 reserved reserved: this bit should always be written with a 0. 6 5 4 3 2 1 0 idl28 idl24 idl20 idl16 idl12 idl8 idl4 internal ds1 idle channel/loopback: the idln bits in this register are used for generating and transmitting a ds1 idle pattern or for setting up a local ds1 loopback for channel n. when register 1eh is written with a code to disconnect the loopback on a channel in this register, and the corre- sponding idln bit is written with a 1, the m13x generates and transmits a ds1 idle pattern in that channel which is determined by the idle code selec- tion bits (idlb and idla in location 02h). when a code to connect a loop- back on a channel in this register is written to register 1eh, and a 1 is written into the corresponding idln bit, the ds1 channel is looped back instead. the loopback is from the receive to the transmit direction. when the idln bit is written with a 0, the ds1 transmit source is from the chan- nel ? s dtn/ctn leads. 14 7 reserved reserved: this bit should always be ignored. 6-0 r2xn (n=7-1) receive ds2 x-bits: the bits in this location indicate the states of the seven received ds2 channel x-bits. 15 7 reserved reserved: this bit should always be written with a 0. 6-0 t2xn (n=7-1) transmit ds2 x-bits: the bits in this location are used to set the states of the seven transmitted ds2 channel x-bits. an x-bit off state is normally a 1. 16 7 6 5 4 3 2 1 0 r3los r3oof r3ais r3idl r3ckf t3ckf xr2 xr1 latched receive alarms/status: the bits in this register location are the same alarm/status bits listed in register location 00h, except the corre- sponding bit latches on with an alarm. bits 1 and 0 are the latched inverses of the two x-bits received. when latched on they are equal to 0. a micro- processor read cycle clears all these bits to their off states. if an alarm state or status condition remains true, the corresponding bit relatches. address bit symbol description www.datasheet.in - 77 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 17 7 6-0 cerror ds2oofn (n=7-1) latched c-bit status/ds2 out of frame bits: the bits in this register are the same bits listed in register location 03h, except the corresponding bit latches on with an alarm. for example, cerror latches to a 1 the first time c1 is 0. a microprocessor read cycle clears all latched bits. if a ds2 oof remains true, the corresponding bit relatches. 18 7-0 test bits transwitch test register: used for transwitch testing. this register must not be written. 19 7 c3clki c-bit parity c3 clock inhibit: a 0 enables the m13x to generate an extra clock pulse in the cckt clock signal for clocking the c3 bit in from external logic. a 1 disables the generation of the c3 clock pulse. this bit must be set to 1 if the feac register 1ch is used to transmit feac codes or if register 07h is used to send a remote loopback request via a double word feac message (lbsel = 1). if this bit is set to 0, then the feac messages are derived from the external c-bit interface. 6-0 test bits transwitch test bits: used for transwitch testing. when this register is written, the values read from these bits must be re-written. 1a 7-5 rhis2- rhis0 receive pmdl status: the following table lists the various status indica- tions associated with the receive pmdl message. the significance of these bits is controlled by control bit rhie (bit 5) in register 3dh. these are unlatched bits that reflect the current status of the receive pmdl processing. codes of 101 and 110 are not defined. when a condition occurs, all three bits are updated at once and are typically set for at least 1 byte time (i.e., 8 receive pmdl bits) after which they are reset to 0. the priority for detecting these alarms is: abort (highest) invalid frame received fcs error received start of message indication valid message received address bit symbol description rhis2 rhis1 rhis0 rhie condition present 0 0 0 x idle condition 0 0 1 x start of message indication 0 1 0 0 valid message received; (fcs checked ok), or the receive fifo needs servicing (full or overflow). 0 1 0 1 valid message received; (fcs checked ok), or the receive fifo needs servicing (half full or more). 0 1 1 x message received with fcs error 1 0 0 x abort message received 1 1 1 x invalid frame received. (i.e., a frame with a non- integral number of bytes or with a number of bytes (after destuffing) less than 5). 1 0 1 x unused code. see note below. 1 1 0 x unused code. (make sure that bit-oriented codes, do not cause these bits to become set). this com- bination of bit settings should never appear. www.datasheet.in - 78 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 1a (cont.) 4-3 rxfs1- rxfs0 receive pmdl fifo status: the following table lists the various fifo sta- tus indications associated with the receive pmdl fifo. these are unlatched bits that indicate the current state of the receive pmdl fifo. when a condition occurs both bits are updated at once. 2-1 txfs1- txfs0 transmit pmdl fifo status: the following table lists the various fifo status indications associated with the transmit pmdl fifo. these are unlatched bits that indicate the current state of the transmit pmdl fifo. when a condition occurs both bits are updated at once. 0 reserved reserved: this bit is reserved and the value read from it must be ignored. 1b 7-0 fmen (n=7-0) ds3 f-bits and m-bits in error counter: a saturating counter that counts the number of ds3 f-bits and ds3 m-bits that are in error since it was last read. the counter is inhibited when ds3 loss of signal or out of frame occurs. the counter is cleared when it is read by the microprocessor. when m13x is low, this counter is 16 bits wide and this address contains the low byte of the counter. the high byte of this counter is written to the cr register (3eh) when this register is read. when m13x is high, this counter is 8 bits wide. address bit symbol description rxfs1 rxfs0 condition present 0 0 normal. pmdl fifo less than half full. 0 1 fifo equal to or more than half full 10fifo full 1 1 fifo overflow txfs1 txfs0 condition present 0 0 normal. pmdl fifo equal to or more than half full 0 1 fifo less than half full 1 0 fifo overflowed (attempt to write to a full fifo) 1 1 fifo underflow. reported only if eom not set when fifo underflows. www.datasheet.in - 79 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 1c 7 6 5-0 exec cont/10 tfeacn (n=6-1) transmit feac word: bit 7 (exec) initiates the feac transmission and also indicates when the transmission is completed. bit 6 (cont/10) con- trols the duration of the feac transmission (1 = continuous, 0 = 10 times). bits 5-0 (tfeacn) constitute the 6-bit variable (xxxxxx) field in the feac word. a feac word is written in the field in the same order of transmission as shown below: the m13x formats and generates the other 1s and zeros that comprise the feac word. a minimum length (send feac word 10 times) message is sent by using the following sequence: write 1 0 x x x x x x (xxxxxx = 6-bit feac word) m13x sends 16-bit feac word 10 times m13x indicates completion by resetting bit 7 (0 0 x x x x x x) a continuous feac word is sent by using the following sequence: write 1 1 x x x x x x (xxxxxx= 6-bit feac word) m13x sends 16-bit feac word continuously write 1 0 y y y y y y (y = don ? t care) m13x terminates feac word transmission. termination is com- pleted when the exec bit is set to 0 by the m13x. transmission must be terminated before another feac word can be loaded and transmitted. note: the c3clki bit in register 19h must be set to a 1 if this register is used to transmit a feac message. address bit symbol description 16-bit feac word 1 1 1 1 1 1 1 1 0 0 x x x x x x x x x x x x bit 7 1ch feac word/ register 1ch relationship www.datasheet.in - 80 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 1d 7 6 5-0 fidl new rfeacn (n=6-1) receive single feac word: bit 7 (fidl) is the feac idle channel indica- tion. it clears whenever a 0 c3 bit is received framing the six-bit variable word. bit 7 cannot be reset by a microprocessor read cycle. bit 6 (new) indicates when a new feac word has been detected. it clears when the register is read. when the m13x lead is high, the new bit will be set under the conditions that cause the new bit to be set in the m13e device. namely, the new bit becomes set when any five consecutive and identical feac messages are received. the new bit will continually be reasserted if it is read and cleared when a continuous constant feac message is received. when the m13x lead is low, the new bit does not become set to one again after it is cleared when a continuous constant feac message is received. bits 5-0 (rfeacn) constitute the variable (xxxxxx) field in the feac word. a received feac word is stored in bits 5-0 with the first bit received in bit 0, as shown below: the following table lists possible feac combinations: notes: 1. there is no buffering for the received feac message. the latest, validated feac message is stored and bit 6 (new) is set to 1 even if the previous message was not read. 2. line loopback activate and deactivate feac codes are not displayed in this register. also the individual line loopback activate and deactivate codewords are not displayed in this register. address bit symbol description 16-bit feac word 1 1 1 1 1 1 1 1 0 0 x x x x x x x x x x x x bit 7 1dh fidl new status 1 0 feac channel idle - no message received since last read cycle 0 1 new message received - feac channel busy 1 1 new message received - feac channel idle www.datasheet.in - 81 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 1e 7 6 5 4 3 2 1 0 exec con/dis reserved llb22 llb21 llb20 llb11 llb10 ds1 local loopback: this register is used in conjunction with registers 10h-13h. bit 7 (exec) initiates the loopback. this bit is reset automatically upon completion of the command. bit 6 (con/dis) connects or discon- nects the specified loopback. bit 5 is reserved and must be written with a 0. bits 4 through 2 (llb2n) select one of seven ds2s. bits 1 and 0 (llb1n) select the ds1 within the ds2 signal. the following table lists the com- mands for generating local loopback: 1f 7-0 reset initialization register: this register location is used to reset and initialize the m13x. after power becomes stable, a f0 hex followed by a 00 hex must be written into this location. address bit symbol description bits 7 6 5 4 3 2 1 0 channel exec con/ dis res. llb22 llb21 llb20 llb11 llb10 all 110000 0 0 clear all 100000 0 0 clear all confirmed 0 0 0 0 0 0 0 0 channel 1 1 1 0 0 0 1 0 0 channel 2 1 1 0 0 0 1 0 1 channels 3 to 27 11000110 to 11011110, llb2 incrementing on llb1=00 channel 28 1 1 0 1 1 1 1 1 clear channel 28 1 0 0 1 1 1 1 1 clear channel 28 confirmed 000111 1 1 www.datasheet.in - 82 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 20 7 1trist tri-state ds1 receive channels: a 1 causes all 28 receive ds1 data (drn) and clock (crn) output leads to be set to a high impedance state. 6 1lossel ds1 loss of signal selection: a 0 selects the receive ds1 channels for loss of signal detection. a 1 selects the transmit ds1 channels for loss of signal detection. the ds1 loss of signals (losn) are reported in register locations 0ch through 0fh. 5 4 1tais1 1tais0 ds1 ais insertion selection: these two bits control the insertion of ais (unframed all 1s) into the 28 ds1 channels on certain ds3 alarm condi- tions that are defined in register location 00h. the following table lists the settings for having various alarm conditions selected to cause ais: for the settings of 1tais1 and 1tais0 other than 0,0, the ds1 clock and data outputs of the m13x go to one level for those cases where a received ds3 alarm condition that is not supposed to produce a receive ds1 ais condition occurs. the xck clock is used as the timebase for generating the ds1 ais clocks. 3 2 1 0 1lbv3 1lbv2 1lbv1 1lbv0 remote loopback options: the following table indicates the various ways the m13x can transmit and receive a ds1 remote loopback request in the m13 or c-bit parity operating modes. the specified condition is trans- mitted for the duration of the loopback request (see register 07h for trans- mission operation): address bit symbol description 1tais1 1tais0 received ds3 alarm conditions 0 0 r3oof, r3ais, r3los, r3ckf 0 1 r3oof, r3ais, r3ckf 1 0 r3los 1 1 no ais insertions note: & = and in the transmit direction, + = or in the receive direction. 1lbv3 1lbv2 1lbv1 1lbv0 loopback type 0000third ds2 c-bit inverted 0001second ds2 c-bit inverted 0010first ds2 c-bit inverted 0011undefined - do not use 0100third ds2 c-bit &/+ (see note) ds2 stuff bit inverted 0101second ds2 c-bit &/+ (see note) ds2 stuff bit inverted 0110first ds2 c-bit &/+ (see note) ds2 stuff bit inverted 0111ds2 stuff bit inverted 1000ds2 stuff bit = 0 1001ds2 stuff bit = 1 1 x 1 x undefined - do not use 1 1 x x undefined - do not use www.datasheet.in - 83 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 21 7-5 reserved reserved: these bits should always be written with a 0. 4 3 2 r3ais2 r3ais1 r3ais0 receive ds3 ais selection: a ds3 ais may be detected with any one of five different criteria. these three bits select the ds3 ais detection mecha- nism that is used for providing an r3ais alarm, as shown in the table below. the c-bits = 0 and x bits = 1 conditions are detected as explained for bits 6 and 7 of address 24h. the other detection conditions are described below. r3ais(2-0) set to 000, 001, and 010 respectively: the framed 1010 pattern detection consists of looking for the 1010 pattern on a per ds3 subframe basis and monitoring for errors in 4-bit groups of the 1010 pattern. the 1010 pattern is accepted as valid if the m13x receives 4 or fewer errored 4-bit groups of the 1010 pattern per ds3 subframe and the 1010 pattern starts with a 1 after each ds3 overhead bit. r3ais(2-0) set to 100: for the unframed 1010 pattern detection the m13x looks for 1010 pattern and declares r3ais if it receives 2 or fewer errored 4-bit groups of the 1010 pattern per ds3 subframe. the m13x will exit the r3ais state if it receives 5 or more errored 4-bit groups of the 1010 pattern per ds3 subframe. if 3 - 4 4-bit groups of the 1010 pattern are errored per ds3 subframe the m13x will exit and reenter the r3ais state. r3ais(2-0) set to 101: the unframed 1111 pattern detection consists of looking for the 1111 pat- tern and monitoring for errors in 4-bit groups of the 1111 pattern. the 1111 pattern is accepted as valid if the m13x receives 4 or fewer errored 4-bit groups of the 1111 pattern out of a total of 168 4-bit groups. address bit symbol description r3ais2 r3ais1 r3ais0 receive ds3 ais selection criterion 0 0 0 framed 1010 pattern c-bits = 0 x-bits disregarded 0 0 1 framed 1010 pattern c-bits = 0 x-bits = 1 0 1 0 framed 1010 pattern c-bits disregarded x-bits disregarded 0 1 1 undefined - do not use 1 0 0 unframed 1010 pattern 1 0 1 unframed all ones pattern 1 1 x undefined - do not use www.datasheet.in - 84 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 21 (cont.) 1 0 t3ais1 t3ais0 transmit ds3 ais selection: a ds3 ais may be generated in one of four ways. the following table selects the ds3 ais generation mechanism: 22 7-0 c1bzn (n=7-0) c1 bit zero counter: a saturating counter that counts the number of c1 bits equal to 0 in both the c-bit parity mode and m13 format mode since the counter was last read. in the m13 format mode the contents of this counter should be disregarded. the counter is inhibited when ds3 loss of signal or out of frame occurs. the counter is cleared when it is read by the micropro- cessor. when lead m13x is low, this counter is 16 bits wide and this address contains the low byte of that counter. the high byte of the counter is written to the cr register (3eh) when this register is read. when lead m13x is high, this counter is 8 bits wide. 23 7-0 men (n=7-0) ds3 m-bits in error counter: a saturating counter that counts the number of m-bits that are in error since the counter was last read. the counter is inhibited when ds3 loss of signal or out of frame occurs. the counter is cleared when it is read by the microprocessor. when lead m13x is low, this counter is 16 bits wide and this address contains the low byte of the counter. the high byte of this counter is written to the cr register (3eh) when this register is read. when lead m13x is high, this counter is 8 bits wide. address bit symbol description note: these bits must be set to 0 when transmitting ds3 idle (see t3idl in register 01h). t3ais1 t3ais0 transmit ds3 ais selection 0 0 ansi defined ais generation note: a 1 must be written to bit 0 of register 01h to set the transmitted ds3 x-bits to 1. 0 1 framed all ones and c-bits set to 1 1 0 unframed 1010 pattern 1 1 unframed all ones pattern www.datasheet.in - 85 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 24 7 aisxeq1 ds3 ais detection: this bit provides a filtered indication of the receive ds3 x-bits being equal to 1. two counters are used to implement this filter, a mod 16 counter cxe1 which counts the receive ds3 x-bit pairs = 11, and a mod 4 counter cxe0 which counts the receive ds3 x-bit pairs = 00. when either counter matures, both counters are reset. the aisxeq1 bit becomes latched when the cxe1 counter matures. this bit is used for determining if the x-bits = 1 condition is met when r3ais2 = 0, r3ais1 = 0, and r3ais0 = 1 in register 21h (ansi ds3 defined ais detection). this is a latched bit, and clears when it is read by the microprocessor. this bit will relatch if the condition that causes this bit to latch is still present. 6aisceq0 ds3 ais detection: this bit provides a filtered indication of the receive ds3 c-bits equal to 0. this bit will be set if the m13x receives 7 contiguous ds3 frames with 30 or fewer ds3 c-bits set to 1. this bit is used for deter- mining if the c bits = 0 condition is met when r3ais2 = 0, r3ais1 = 0, and r3ais0 = x, where x means don ? t care. this is a latched bit, and clears when it is read by the microprocessor. this bit will relatch if the condition that causes this bit to latch is still present. 5test bit test bit: used for diagnostic purposes. this bit must always be ignored. 4test bit test bit: used for diagnostic purposes. this bit must always be ignored. 3test bit test bit: used for diagnostic purposes. this bit must always be ignored. 2test bit test bit: used for diagnostic purposes. this bit must always be ignored. 1reserved reserved: this bit must always be ignored. 0sef severely errored frame indication: a 1 indicates a severely errored frame (sef) has been detected. a sef is defined as 3 out of 16 f-bits are in error, utilizing a sliding window of 16 f-bits. this is a latched bit, and clears when it is read by the microprocessor. this bit will relatch if the con- dition that causes it to latch is still present. 25 7 6 5 4 3 2 1 0 irlball irlb25 irlb21 irlb17 irlb13 irlb9 irlb5 irlb1 receive loopback interrupt requests: the bits in these registers are interrupt request bits for the corresponding remote loopback request bits in register 08h. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm condition, or both. if the corresponding interrupt request mask bit is set to a 1 in regis- ter 2eh then the int/irq lead goes active to signal an interrupt request to the external microprocessor when a bit in these registers becomes set to 1. a microprocessor read cycle clears all set interrupt request bits in the regis- ter that is read. 26 7 6 5 4 3 2 1 0 irlbds3 irlb26 irlb22 irlb18 irlb14 irlb10 irlb6 irlb2 receive loopback interrupt requests: the bits in these registers are interrupt request bits for the corresponding remote loopback request bits in register 09h. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm condition, or both. if the corresponding interrupt request mask bit is set to a 1 in regis- ter 2fh then the int/irq lead goes active to signal an interrupt request to the external microprocessor when a bit in these registers becomes set to 1. a microprocessor read cycle clears all set interrupt request bits in the regis- ter that is read. address bit symbol description www.datasheet.in - 86 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 27 7 irnew new feac message interrupt request bit: the new condition is defined as having received a new feac message. a new feac mes- sage is understood to have been received when 5 consecutive and identi- cal feac messages have been received. the new feac condition is exited after a new feac message has been declared. when this bit and its corresponding interrupt request mask bit in register 30h are both set to 1, the int/irq lead is driven active. a microprocessor read cycle clears a set interrupt request bit. the rise and fall bits in register 3fh control whether this interrupt request bit is set on the entrance or exit of an alarm condition, or both. care must be taken by the end user to ensure that the rx feac register (1dh) is read within 8.5 ms (16 x 5 ds3 frames or 5 feac message times) from the onset of this interrupt request to ensure that the feac message that caused this interrupt does not get overwritten with a possible new feac message. 6 5 4 3 2 1 0 irlb27 irlb23 irlb19 irlb15 irlb11 irlb7 irlb3 receive loopback interrupt requests: the bits in these registers are interrupt request bits for the corresponding remote loopback request bits in register 0ah. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm con- dition, or both. if the corresponding interrupt request mask bit is set to a 1 in register 30h then the int/irq lead goes active to signal an interrupt request to the external microprocessor when a bit in these registers becomes set to 1. a microprocessor read cycle clears all set interrupt request bits in the register that is read. 28 7 irsef severely errored frame interrupt request bit: a severely errored frame is defined as receiving 3 or more ds3 f-bits in error in a sliding window of 16 ds3 f-bits. an sef defect is terminated when the receive ds3 signal is in frame and there are fewer than 3 ds3 f-bit errors in 16 consecutive f-bits (ansi t1.231 sec. 7.1.2.2.2). when this bit and its corresponding interrupt request mask bit in register 31h are both set to 1, the int/irq lead is driven active. a microprocessor read cycle clears a set interrupt request bit. the rise and fall bits in register 3fh have no effect on the functioning of this interrupt. 6 5 4 3 2 1 0 irlb28 irlb24 irlb20 irlb16 irlb12 irlb8 irlb4 receive loopback interrupt requests: the bits in these registers are interrupt request bits for the corresponding remote loopback request bits in register 0bh. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm con- dition, or both. if the corresponding interrupt request mask bit is set to a 1 in register 31h then the int/irq lead goes active to signal an interrupt request to the external microprocessor when a bit in these registers becomes set to 1. a microprocessor read cycle clears all set interrupt request bits in the register that is read. 29 7 6 5 4 3 2 1 0 irr3los irr3oof irr3ais irr3idl irr3ckf irt3ckf irxr2 irxr1 ds3 receive alarms/status interrupt requests: the bits in this register location are interrupt request bits for the alarm/status bits listed in register location 00h. when a bit in this register and its corresponding interrupt request mask bit in register 32h are both set to 1, the int/irq lead is driven active. a microprocessor read cycle clears a set interrupt request bit. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm condition, or both. address bit symbol description www.datasheet.in - 87 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 2a 7 6-0 ircerror irds2oofn (n=7-1) latched c-bit status/ds2 out of frame interrupt request bits: the bits in this register location are interrupt request bits for the alarm/status bits listed in register location 03h. when a bit in this register and its corre- sponding interrupt request mask bit in register 33h are both set to 1, the int/irq lead is driven active. a microprocessor read of the register clears all set interrupt request bits. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm condition, or both. 2b* 7 irfcss fcs error counter saturated interrupt request: this bit becomes set when the rx fcs error counter (3bh) saturates. 6irabts abort counter saturated interrupt request: this bit becomes set when the rx abort counter (3ch) saturates. 5irfbs febe performance/ds3 f-bit and m-bit error counter saturated inter- rupt request: this bit becomes set when the febe performance/ds3 f- bit and m-bit error counter (04h) saturates. 4 ircps c-bit parity performance/number of frames counter saturated inter- rupt request: this bit becomes set when the c-bit parity performance/ number of frames counter (05h) saturates. 3irpps p-bit parity performance counter saturated interrupt request: this bit becomes set when the p-bit parity performance counter (06h) saturates. 2irfmes ds3 f-bits and m-bits in error counter saturated interrupt request: this bit becomes set when the ds3 f-bits and m-bits in error counter (1bh) saturates. 1 irc1bzs c1 bit equal to zero counter saturated interrupt request: this bit becomes set when the c1 bit equal to zero counter (22h) saturates. 0irmes ds3 m-bits in error counter saturated interrupt request: this bit becomes set when the ds3 m-bits in error counter (23h) saturates. * note: the bits in register 2bh are latched bits, and they all clear to 0 when it is read by the microprocessor. if a bit and its corresponding interrupt mask bit in register 34h are both set to a 1, then the int/irq lead goes active to sig- nal an interrupt request to the external microprocessor. the rise and fall bits in register 3fh control whether these interrupt request bits are set on the entrance or exit of an alarm condition, or both. address bit symbol description www.datasheet.in - 88 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 2c 7-5 irrhis2- irrhis0 receive pmdl interrupt request: the following table lists the various interrupt status indications associated with the receive pmdl message. the significance of these bits is controlled by control bit rhie (bit 5) in reg- ister 3dh. these are latched bits that clear when read by the microprocessor. if a bit in this register is set to a 1 and the corresponding interrupt mask bit in reg- ister 35h is set to a 1, then the int/irq lead goes active to signal an inter- rupt request to the external microprocessor. codes of 110 and 101 are not defined. when a condition occurs all three bits are updated at once. for instance, when a start of message occurs, the bits are set to 001, and when an end of message is received the bits will be changed from 001 to 010. the bits are never forced to 000 by the internal logic. they only get set to 000 when a read is performed. the priority for detecting these alarms is: abort (highest) invalid frame received fcs error received start of message indication valid message received address bit symbol description irrhis2 irrhis1 irrhis0 rhie condition present 0 0 0 x idle condition 0 0 1 x start of message indication 0 1 0 0 valid message received; (fcs checked ok), or the receive fifo needs servicing (full or overflow). 0 1 0 1 valid message received; (fcs checked ok), or the receive fifo needs servicing (half full or more). 0 1 1 x message received with fcs error 1 0 0 x abort message received 1 1 1 x invalid frame received. (i.e., frame with non-inte- gral number of bytes or with number of bytes (after destuffing) less than 5). 1 0 1 x unused code. 1 1 0 x unused code. www.datasheet.in - 89 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 2c (cont.) 4-3 irrxfs1- irrxfs0 receive pmdl fifo interrupt request: the following table lists the vari- ous fifo status indications associated with the receive pmdl fifo. these are latched bits that clear when the register is read by the micropro- cessor. if a bit in this register is set to a 1 and the corresponding interrupt mask bit in register 35h is set to a 1, then the int/irq lead goes active to signal an interrupt request to the external microprocessor. when a condi- tion occurs both bits are updated at once. 00 is never forced by the internal logic. these bits are only set to 00 when a read is performed. 2-1 irtxfs1- irtxfs0 transmit pmdl fifo interrupt request: the following table lists the vari- ous fifo status indications associated with the transmit pmdl fifo. these are latched bits that clear when the register is read by the micropro- cessor. if a bit in this register is set to a 1 and the corresponding interrupt mask bit in register 35h is set to a 1, then the int/irq lead goes active to signal an interrupt request to the external microprocessor. when a condi- tion occurs both bits are updated at once. 00 is never forced by the internal logic. these bits are only set to 00 when a read is performed. 0irthis transmit pmdl interrupt request: a 1 indicates that the transmit pmdl fifo needs servicing, either because the message is completed, or because the transmit pmdl fifo transitioned from more than half full to half full, depending on the thie control bit setting. this is a latched bit, and clears when the register is read by the microprocessor. if this bit is set to a 1 and the corresponding interrupt mask bit in register 35h is set to a 1, then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 2d 7-0 reserved reserved: these bits are reserved and must always be ignored. address bit symbol description irrxfs1 irrxfs0 condition present 0 0 normal. pmdl fifo less than half full. 0 1 fifo equal to or more than half full 1 0 fifo full 1 1 fifo overflow irtxfs1 irtxfs0 condition present 0 0 normal. pmdl fifo equal to or more than half full 0 1 fifo less than half full 1 0 fifo overflowed (attempt to write to a full fifo) 1 1 fifo underflowed. reported only if eom is not set when fifo underflows. www.datasheet.in - 90 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 2e 7 6 5 4 3 2 1 0 mirlball mirlb25 mirlb21 mirlb17 mirlb13 mirlb9 mirlb5 mirlb1 receive loopback interrupt request masks: if a bit in this register and its corresponding interrupt request bit in register 25h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 2f 7 6 5 4 3 2 1 0 mirlbds3 mirlb26 mirlb22 mirlb18 mirlb14 mirlb10 mirlb6 mirlb2 receive loopback interrupt request masks: if a bit in this register and its corresponding interrupt request bit in register 26h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 30 7 mirnew new feac message interrupt request mask bit: if this bit and its corre- sponding interrupt request bit in register 27h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 6 5 4 3 2 1 0 mirlb27 mirlb23 mirlb19 mirlb15 mirlb11 mirlb7 mirlb3 receive loopback interrupt request masks: if a bit in this register and its corresponding interrupt request bit in register 27h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 31 7 mirsef severely errored frame interrupt request mask bit: if this bit and its corresponding interrupt request bit in register 28h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 6 5 4 3 2 1 0 mirlb28 mirlb24 mirlb20 mirlb16 mirlb12 mirlb8 mirlb4 receive loopback interrupt request masks: if a bit in this register and its corresponding interrupt request bit in register 28h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 32 7 6 5 4 3 2 1 0 mirr3los mirr3oof mirr3ais mirr3idl mirr3ckf mirt3ckf mirxr2 mirxr1 ds3 receive alarms/status interrupt request masks: if a bit in this reg- ister and its corresponding interrupt request bit in register 29h are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. address bit symbol description www.datasheet.in - 91 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 33 7 6-0 mircerror mirds2oofn (n=7-1) latched c-bit status/ds2 out of frame interrupt request mask bits: if a bit in this register and its corresponding interrupt request bit in register 2ah are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 34 7 mirfcss fcs error counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 6mirabts abort counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 5mirfbs febe performance/ds3 f-bit and m-bit error counter saturated inter- rupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 4mircps c-bit parity performance/number of frames counter saturated inter- rupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 3mirpps p-bit parity performance counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 2mirfmes ds3 f-bits and m-bits in error counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 1 mirc1bzs c1 bit zero counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 0mirmes ds3 m-bits in error counter saturated interrupt request mask: if this bit and its corresponding interrupt request bit in register 2bh are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 35 7-5 mirrhis2- mirhis0 receive pmdl interrupt request masks: if a bit and its corresponding interrupt request bit in register 2ch are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microproces- sor. 4-3 mirrxfs1- mirrxfs0 receive pmdl fifo interrupt request masks: if a bit and its corre- sponding interrupt request bit in register 2ch are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. address bit symbol description www.datasheet.in - 92 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 35 (cont.) 2-1 mirtxfs1- mirtxfs0 transmit pmdl fifo interrupt request masks: if a bit and its corre- sponding interrupt request bit in register 2ch are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microprocessor. 0mirthis transmit pmdl interrupt request mask: if this bit and its corresponding interrupt request bit in register 2ch are both set to a 1 then the int/irq lead goes active to signal an interrupt request to the external microproces- sor. 36 7-0 reserved reserved: these bits are reserved and must always be written with 0s. 37 7-0 tx pmdl fifo transmit pmdl fifo: the byte written into this location is written into the transmit pmdl fifo. bit 0 corresponds to the first bit transmitted in an hdlc message byte. 38 7-0 rx pmdl fifo receive pmdl fifo: a read cycle for this location transfers one byte from the receive pmdl fifo to the data bus. bit 0 corresponds to the first bit received in the hdlc message. at initialization, the receive pmdl fifo must be cleared by reading this location the number of times indicated by the rx pmdl fifo depth register (register 3ah) or until the rx pmdl fifo depth register becomes 0. 39 7-0 rx pmdl message length receive pmdl message length: this register is loaded with the number of bytes in the last received frame if an end of message, abort, invalid frame, or message received with bad fcs event occurs. the microproces- sor must read this value before the end of another complete frame is received. this register clears when read. the receive pmdl logic never loads this register with a 0 when a valid pmdl frame is received (this is done so that if a long frame is received, and the receive pmdl message length ends up exceeding 255, and the irrhis(2-0) bits get set to 010 to indicate a fifo fill condition, then it can be known if an end of message was really received.) 3a 7-0 rx pmdl fifo depth hdlc fifo depth: this register indicates the number of data bytes present in the receive pmdl fifo. the value is in binary. for example, the value 0000 0000 indicates that the fifo is empty, while a value 0111 1111 indicates that 127 bytes are present. this value is not reset when a new frame is received. the previous frame length is stored in rx pmdl mes- sage length, (bits 7- 0) in register 39h, which is updated every time a new complete frame (good or errored) is received. this register value is decreased by microprocessor reads of the rx pmdl fifo register (regis- ter 38h) only. at initialization, this location should read out as 00h. if it does not, repeated reads of the rx pmdl fifo register should be performed until it does. 3b 7-0 rx fcs error counter rx fcs error counter: a 16-bit saturating counter that counts the number of pmdl messages that contained fcs errors. to read all 16 bits, read this location to get the low byte and then read the common register location (3eh) immediately after to get the high byte. the contents of this counter should be disregarded when m13mode = 1 or ehr = 0 or lead m13x is high or floating. the counter is inhibited when ds3 loss of signal, out of frame, ais, or idle occurs. the counter is cleared when it is read by the microprocessor. single counts are not lost during a read cycle. when this counter saturates, an interrupt request bit (irfcss) is set in register 2bh. address bit symbol description www.datasheet.in - 93 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 3c 7-0 rx abort counter receive abort counter: a 16-bit saturating counter that counts the num- ber of abort sequences (1111111) that were detected. to read all 16 bits, read this location to get the low byte and then read the common register location (3eh) immediately after to get the high byte. the contents of this counter should be disregarded when m13mode = 1 or ehr = 0 or lead m13x is high or floating. the counter is inhibited when ds3 loss of signal, out of frame, ais, or idle occurs. the counter is cleared when it is read by the microprocessor. single counts are not lost during a read cycle. when this counter saturates, an interrupt request bit (irabts) is set in register 2bh. 3d 7 djb djb control: when this bit is set to 0, the internal dejitter buffers (djbs) are bypassed and held in reset. the gapped receive ds1 clock and data are output on the receive ds1 clock and data outputs (cr1-28 and dr1- 28). when this bit is set to a 1, the djbs are taken out of reset and the receive ds1 clock and data are passed through the djbs before being out- put on cr1-28 and dr1-28. also if a local ds1 loopback is enabled via registers 10h-13h and 1eh, while this bit is set to 1, the looped back ds1 data is dejittered. 6ipolal interrupt polarity: the setting of this bit determines the polarity of the int/ irq lead when that lead is driven active. when this bit is set to a 1, the polarity of the int/irq lead is active low. otherwise, the polarity is active high. 5rhie receive half full interrupt enable: this bit controls the irrhis(2-0) interrupt request bit logic to allow interrupts to occur for two different fifo fill conditions in the ? 010 ? state. a 1 enables the receive hdlc controller to generate an interrupt when the receive pmdl fifo is half full or more, or has detected an end of message. when set to 0, the hdlc controller gen- erates an interrupt when a receive pmdl fifo full or overflow has occurred, or at the end of the message. 4ehr enable hdlc receive controller: a 1 enables the hdlc receive control- ler. after flag detection and zero bit destuffing, the receive bytes from the pmdl c-bits in the c-bit parity format ds3 frame only are written into a receive fifo for a microprocessor read access via register 38h (receive pmdl fifo). a 0 disables the hdlc controller and disables the hdlc receive interrupts. 3reserved reserved: this bit is reserved and must always be written with a 0. 2eom transmit end of message: a 1 instructs the hdlc controller that the transmit pmdl fifo contains the last byte in the message. when the fifo has emptied, the fcs is calculated and transmitted and then this bit is cleared. 1thie transmit half full interrupt enable: this bit controls the irthis interrupt request bit logic to allow interrupts to occur at the transmit pmdl fifo transition from more than half empty to half empty or message complete only. a 1 enables the transmit hdlc controller to generate an interrupt when the transmit pmdl fifo transitions from more than half empty to half empty or has detected an end of message. when set to 0, the hdlc con- troller generates an interrupt only at the end of the message, or when a fifo underflow has occurred. address bit symbol description www.datasheet.in - 94 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet 3d (cont.) 0 eht enable hdlc transmit controller: a 1 enables the transmit pmdl con- troller. the pmdl c-bits in the transmit ds3 frame are derived from the transmit pmdl controller. the transmitter will send flags when the transmit pmdl fifo is empty. the bytes are formatted into a message when the transmit pmdl fifo has bytes present, which is done by loading the tx pmdl fifo register (register 37h) repeatedly with the byte content of the message to be sent. at the end of the message, a fcs is calculated and transmitted. a 0 disables the transmit pmdl controller, clears the transmit pmdl fifo, and disables the pmdl transmit interrupts. in this case, the pmdl c-bits in the transmit ds3 frame are derived from the external trans- mit c-bit interface (m13mode = 0) or from the internal stuffing logic (m13mode = 1). 3e 7-0 cr common register for high byte of 16-bit counters: when the low byte of a 16-bit counter is read, its high byte is simultaneously written to this reg- ister and preserved for later access. in this way, the high byte and low byte values correspond to the same instant in time. 3f 7-2 reserved reserved: these bits are reserved and must always be written with a 0. 1rise rising edge sets interrupt request bits: this control bit works in con- junction with the fall control bit (described below) for controlling the alarm status bit transition used for setting the interrupt request bits. rise=1 causes setting of the interrupt request bits on the 0 to 1 transition of the alarm. register 2ch is not affected by the setting of this bit. the interrupt request bits in register 2ch are always set on the rising edge of the alarm condition. 0fall falling edge sets interrupt request bits: this control bit works in con- junction with the rise control bit (described above) for controlling the alarm status bit transition used for setting the interrupt request bits. fall=1 causes setting of the interrupt request bits on the 1 to 0 transition of the alarm. register 2ch is not affected by the setting of this bit. the interrupt request bits in register 2ch are always set on the rising edge of the alarm condition. address bit symbol description rise fall action 0 0 the appropriate interrupt request bits are disabled from being set. 0 1 the appropriate interrupt request bits become set when an alarm/condition is removed. 1 0 the appropriate interrupt request bits become set when an alarm/condition is entered. 1 1 the appropriate interrupt request bits become set when an alarm/condition is either entered or removed. www.datasheet.in - 95 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet application diagram a typical channelized t3 application is shown below. figure 26. example channelized t3 application transwitch has a ? channelized t3 reference design ? technical manual, document number txc-21114-tm1, available for use with this device. it may be viewed or printed from the ? products/m13x ? page of the transwitch wold wide web site (www.transwitch.com). m13x TXC-03305 art/arte/dart txc-02020/ ds3 t1fx8 txc-03108 t1fx8 txc-03108 } ds0 applications } 2.048 mbit/s mvip: ds0, sig, clk, data cross point (ds0) cross point (ds0) ds1 liu liu ds1 ds1 ds1 ds1 ds1 txc-02021/ txc-02030 www.datasheet.in - 96 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet package information the m13x device is available in two package formats. a 208-lead small outline plastic ball grid array package suitable for surface mounting is illustrated in figure 27. a 208-lead plastic quad flat package, suitable for sur- face mounting, is shown in figure 28. . figure 27. m13x TXC-03305 208-lead plastic ball grid array package 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 trpnmlkjhgfedcb b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 (a3) a a1 dimension (note 1) min max notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. 3. size of array: 16 x 16, jedec code mo-151/b-aae-1 a a1 a2 1.35 0.30 0.75 1.75 0.50 0.85 a3 (ref.) 0.36 b 0.40 0.60 d17.00 d1 (bsc) 15.00 d2 15.00 15.70 e17.00 e1 (bsc) 15.00 e2 15.00 15.70 e (bsc) 1.00 bottom view transwitch TXC-03305aiog 16 a www.datasheet.in - 97 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet figure 28. m13x TXC-03305 208-lead plastic quad flat package 156 105 104 53 1 208 25.50 sq 28.00 0.10 sq 30.60 0.25 sq 4.07 (max) 0.25 (min) see detail ? a ? 0.60 + 0.15 0 o -7 o detail ? a ? 157 52 lead #1 index transwitch 0.20 0.09 0.50 typ 0.17 (min) 0.27 (max) see details ? b ? and ? c ? detail ? b ? detail ? c ? note : all dimensions shown are in millimeters and are nominal unless otherwise indicated. TXC-03305aipq 3.60 3.20 -0.10 www.datasheet.in - 98 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet ordering information part number: TXC-03305aiog 208-lead small outline plastic ball grid array package. part number: TXC-03305aipq 208-lead plastic quad flat package. related products txc-02020, art vlsi device (advanced sts-1/ds3 receiver/transmitter). art performs the transmit and receive line interface functions required for transmission of sts-1 (51.840 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02021, arte vlsi device (advanced sts-1/ds3 receiver/transmitter). arte has the same functionality as art, plus extended features. txc-02030, dart vlsi device (advanced e3/ds3 receiver/transmitter). dart performs the transmit and receive line interface functions required for transmission of e3 (34.368 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-20153g, ds3/sts-1 line interface module (ds3lim-sn). complete and compact analog-to- digital interface that converts b3zs-encoded ds3 or sts-1 line signals to and from nrz data and clock signals. packaged as 2.6 inch x 1.0 inch 50-lead dip. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). this device is similar to the syn155. it has both clock and data outputs on the line side. txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). this is a dual-mode device, which can be configured either to emulate the txc-03001 device or to provide additional capabilities. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this is a dual- mode device, which can be configured either to emulate the txc-03003 device or to provide additional capabilities. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). this device provides extended features relative to the 84-lead txc-03001 and txc-03001b sot-1 devices, and it has a 144-lead package. txc-03103, qt1f- plus vlsi device (quad t1 framer- plus ). a 4-channel framer for voice and data applications. this device handles all logical interfacing functionality to a t1 line. it has extended features relative to the qds1f device. requires +5.0 v power supply. txc-03108, t1fx8 vlsi device (8-channel t1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfacing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-03452b l3m vlsi device (level 3 mapper/desynchronizer) - l3m maps a ds3 or e3 signal into an sdh/sonet signal formatted for stm-n (vc-3 via tu-3) or sts-n (via sts-1 spe). txc-04201b, ds1mx7 vlsi device (ds1 mapper 7-channel). maps seven 1.544 mbit/s ds1 signals into any seven selected asynchronous or byte-synchronous mode vt1.5 or tu-11 virtual tributaries carried in a sonet or sdh synchronous payload envelope. www.datasheet.in - 99 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet txc-04251, qt1m vlsi device (quad ds1 to vt1.5 or tu-11 async mapper-desync). interconnects four ds1 signals with any four asynchronous mode vt1.5 or tu-11 tributaries carried in sonet sts-1 or sdh au-3 rate payload interface. txc-05150, cdb vlsi device (cell delineation block). provides cell delineation for atm cells carried in a physical line at rates of 1.544 to 155 mbit/s. txc-06101, phast-1 vlsi device (sonet sts-1 overhead terminator). this device provides features similar to those of the txc-03011 sot-1e device, but it operates from a power supply of 3.3 volts rather than 5 volts. www.datasheet.in - 100 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations ansi (u.s.a.): american national standards institute tel: (212) 642-4900 11 west 42nd street fax: (212) 302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: (650) 949-6700 suite 304 fax: (650) 949-6705 mountain view, ca 94040 web: www.atmforum.com atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium atm forum asia-pacific office hamamatsu-cho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsu-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (314) 726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: (314) 726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france www.datasheet.in - 101 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (508) 650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 building 4 / section d fax: (215) 697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: (503) 693-6232 (outside u.s.a.) hillsboro, or 97124 fax: (503) 693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-core (within u.s.a.) attention - customer service tel: (908) 699-5800 (outside u.s.a.) 8 corporate place fax: (908) 336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsu-cho suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo www.datasheet.in - 102 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet list of data sheet changes this change list identifies those areas within this updated m13x data sheet that have significant differences relative to the previous and now superseded m13x data sheet: updated m13x data sheet: ed. 4, september 2000 previous m13x data sheet: preliminary ed. 3, april 2000 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. all removed all ? preliminary ? indications from document. 2-3 changed table of contents and list of figures. 23 added last row to the absolute maximum ratings and environmental limitations table that states the latch-up specification. 95 added reference to the channelized t3 reference design in the applications section. 98 changed reference to txc-20153d in related products section to txc-20153g. 100 -101 changed standards documentation sources section. 102 changed list of data sheet changes section. www.datasheet.in - 103 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet - note - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, software perfor- mance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellec- tual property right of transwitch covering or relating to any combination, machine, or process in which such semicon- ductor products or services might be or are used. www.datasheet.in - 104 - transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 www.datasheet.in - 105 - TXC-03305-mb ed. 4, september 2000 m13x TXC-03305 data sheet documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: _________________________________________________________________________________ company: __________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: _________________________________________________________________________________ city/state/zip: ___________________________________________________________________________ if located outside u.s.a., please add - country: ________________ postal code: ____________________ telephone: _______________________ ext.: ____________ fax: __________________________ e-mail: _______________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. www.datasheet.in please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required www.datasheet.in |
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